Formal verification: where to use it and why
Lawrence Loh, Jasper Design Automation
(07/10/2006 9:00 AM EDT), EE Times
(07/10/2006 9:00 AM EDT), EE Times
With innovations in technologies and methodology, the benefits of formal functional verification apply in many more areas. If we understand the characteristics of areas with high formal applicability, we can identify not only which blocks are good candidates, but also what portions or functionalities of the blocks will give the greatest return on the time and effort invested. Today, formal verification can be more valuable applied partially within blocks by choosing the functions that have the highest return.
To read the full article, click here
Related Semiconductor IP
- UCIe Chiplet PHY & Controller
- MIPI D-PHY1.2 CSI/DSI TX and RX
- Low-Power ISP
- eMMC/SD/SDIO Combo IP
- DP/eDP
Related White Papers
- Formal Verification Has It Covered!
- Basics of SRAM PUF and how to deploy it for IoT security
- Agile Analog's Approach to Analog IP Design and Quality --- Why "Silicon Proven" is NOT What You Think
- The pitfalls of mixing formal and simulation: Where trouble starts
Latest White Papers
- Achieving Lower Power, Better Performance, And Optimized Wire Length In Advanced SoC Designs
- The pivotal role power management IP plays in chip design
- What tamper detection IP brings to SoC designs
- Analyzing Modern NVIDIA GPU cores
- RISC-V in 2025: Progress, Challenges,and What’s Next for Automotive & OpenHardware