Formal-based methodology cuts digital design IP verification time

By David Vincenzoni, STMicroelectronics
EDN (December 06, 2019)

When we talk about the signoff of digital IP, we are referring to the full verification of a block. Every feature listed in a device's datasheet requires verification. Furthermore, every register transfer language (RTL) statement, branche, and expression also needs verification. Only when the functional (features’ check) and RTL code coverage reaches 100%, the IP is signed-off. To get there, we can consider two different modes to reach the target: the universal verification methodology (UVM) approach (classical methodology) and the formal-based approach (new methodology). Here's how the formal-based approach can significantly reduce verification time.

Classical methodology

For many years, we've used UVM-SV/UVMe methodologies for the verification of digital IPs. This approach is based on complex object/aspect-oriented languages for building constrained-random tests to verify digital blocks and discover bugs. With this method, we can check the features of our block and run hundreds of tests by simply randomizing the data generation, which helps us find the corner conditions and/or dead lock.

The developing of verification environment of a digital IP can be split in the following tasks:

• UVM test bench developing (verification IPs, scoreboards, checkers)
• UVM registers developing (verification of configuration and status registers)
• UVM tests developing (verification of functional features)
• Run of constrained-random tests (the UVM tests runs many times with randomized data)
• Code & functional coverage extraction
• Refinement of coverage by creating new tests and/or increasing the randomized runs

Sometimes SystemVerilog Assertions (SVAs) are added in the test bench to check specific conditions such as the relationship between handshake signals.

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