Facilitating at-speed test at RTL (Part 2)
Dr. Ralph Marlett, Kiran Vittal, Atrenta Inc.
4/20/2011 2:15 AM EDT
Part 1 of this series discusses the problems with at-speed testing, and the various defect models and manufacturing test techniques. This part will tackle at-speed timing closure rules and at-speed coverage. It also looks into the at-speed coverage estimation and diagnosis of SpyGlass-DFT DSM.
The SpyGlass-DFT DSM product provides timing closure analysis and RTL testability for deep subµm (DSM) defects associated with at-speed testing. It is touted to provide accurate RTL fault coverage estimation for transition delay testing, together with diagnostics for low fault coverage, early in the design flow.

Figure 1: Complete RTL analysis solution for stuck-at and at-speed testing.
To access the full Design Article by Atrenta Inc. (in PDF Format), click here.
Read also:
Facilitating at-speed test at RTL (Part 1)
About the authors:
. Dr. Ralph Marlett, Product Director, Atrenta Inc.
. Kiran Vittal, Product Marketing Director, Atrenta Inc.
Courtesy of EE Times India
Related Semiconductor IP
- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
- 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
- 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
- 1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
- Specialed 20V Analog I/O in TSMC 55nm
Related White Papers
- Facilitating at-speed test at RTL (Part 1)
- Moving DFT to RTL overcomes test vector issues
- Static Checks for Power Management at RTL
- Power analysis of clock gating at RTL