Enable IoT ASIC Design Using Platforms
Pradeep Sukumaran, Sr. Solutions Architect, Open-Silicon
EDN (January 07, 2016)
The Internet of Things (IoT) hype is now getting real. This, in turn, is creating the opportunity to move from off-the-shelf chip designs to custom silicon. The key to creating cost-effective, custom silicon for the IoT will be the platform approach.
It is fair to say that IoT is now living up to the hype. There has been a significant uptick in activity over the past year with the IoT ecosystem, the end customers, the hardware and software vendors, the system integrators and the startup community. Yes, IoT implementations are definitely happening, although not at the same rate as first expected, and certainly not the 50 billion devices or a trillion sensors by 2020. Nevertheless, it is an encouraging sign for ASIC design companies as they become an important and differentiating cog of the IoT supply chain.
Historically the industry has been churning out custom silicon for the cloud side of IoT for years, specifically in the networking, telecommunication, storage and computing arenas. However, devices on the edge of the IoT network have, so far, been designed using stock components rather than custom silicon. Using a platform approach to custom silicon design can substantially enhance functionality and offer greater design flexibility.
An IoT edge device typically performs three functions: sensing/actuating, processing and communication. Depending on various factors, like cost, schedule and application, a custom silicon implementation in these IoT edge devices could be a low-end/low-cost, mid-level or highly integrated solution. Below is a representation of typical ASIC configurations of each type. In all of these cases, ultra-low power is a default requirement.
To read the full article, click here
Related Semiconductor IP
- NPU IP Core for Mobile
- NPU IP Core for Edge
- Specialized Video Processing NPU IP
- HYPERBUS™ Memory Controller
- AV1 Video Encoder IP
Related White Papers
- Usage of Multibit Flip-Flop and its Challenges in ASIC Physical Design
- A Heuristic Approach to Fix Design Rule Check (DRC) Violations in ASIC Designs @7nm FinFET Technology
- Increase battery life of Consumer Products using architecture simulation
- How to Design SmartNICs Using FPGAs to Increase Server Compute Capacity
Latest White Papers
- Transition Fixes in 3nm Multi-Voltage SoC Design
- CXL Topology-Aware and Expander-Driven Prefetching: Unlocking SSD Performance
- Breaking the Memory Bandwidth Boundary. GDDR7 IP Design Challenges & Solutions
- Automating NoC Design to Tackle Rising SoC Complexity
- Memory Prefetching Evaluation of Scientific Applications on a Modern HPC Arm-Based Processor