Embedded FPGA: Changing the Way Chips Are Designed
Learn how embedded FPGAs work and what advantages they offer.
Geoff Tate, Flex Logix
allaboutcircuits.com (January 4, 2017)
One of the most critical problems chip designers face today is having to reconfigure RTL at any point in the design process, even in-system. Unfortunately, chip designers have no way of knowing if they will have to do this until it is too late. Any changes at that point end up costing millions of dollars and delaying projects by months.
With embedded FPGA, this problem goes away. Chip designers can finally go into a project knowing they have the flexibility to change RTL at any time during the project, something that has never been possible before.
Because embedded FPGA is a new technology, we will first highlight how it differs from standard FPGAs, which have been around for decades. Basically, an embedded FPGA is an IP block that allows a complete FPGA to be incorporated into an SoC or any kind of integrated circuit. Just as RAM, SERDES, PLL, and processors transitioned from standalone chips to routine IP blocks, FPGA is now also an IP block.
To read the full article, click here
Related Semiconductor IP
- eFPGA on GlobalFoundries GF12LP
- eFPGA IP — Flexible Reconfigurable Logic Acceleration Core
- Heterogeneous eFPGA architecture with LUTs, DSPs, and BRAMs on GlobalFoundries GF12LP
- eFPGA Soft IP
- Radiation-Hardened eFPGA
Related Articles
- Make SoCs flexible with embedded FPGA
- High Density FPGA Package BIST Technique
- A tutorial on tools, techniques, and methodology to improve FPGA designer productivity
- How to choose an RTOS for your FPGA and ASIC designs
Latest Articles
- An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS
- A Persistent-State Dataflow Accelerator for Memory-Bound Linear Attention Decode on FPGA
- VMXDOTP: A RISC-V Vector ISA Extension for Efficient Microscaling (MX) Format Acceleration
- PDF: PUF-based DNN Fingerprinting for Knowledge Distillation Traceability
- TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-up Cluster Design with High Bandwidth Main Memory Link