Efficient analysis of CDC violations in a million gate SoC, part 1
Sanymi Gupta , Aniruddha Gupta & Ankush Sethi (Freescale)
EDN (January 17, 2014)
Configuration of SoC specific logic
There is SoC specific logic (in addition to IPs) which is configured initially through software before the IPs are interacting with each other. A typical case could be as shown below (in Fig. 4). Here, we have a provision to use hardware trigger from timer module to ADC. Clocks of both the module are synchronous. However, if we don’t want to use hardware trigger and want to go only for software trigger for ADC we need to constrain the input of ADC based on configuration of mux select through general purpose register. Suppose the general purpose register is working at clk3 which is asynchronous to clk2 of ADC. The CDC tool will show a violating path from clk3 to clk2 but we can waive this path as we will program initially the select of the mux and then later we will use the ADC. So, this becomes a static signal when it is used.
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