Early Interactive Short Isolation for Faster SoC Verification
By Ritu Walia, Siemens (December 4, 2024)
In modern semiconductor design, shrinking technology nodes and increasing circuit complexity make layout versus schematic (LVS) verification more challenging. One of the most common and critical errors designers find during LVS runs is shorted nets. Identifying and isolating these shorts early in the process is essential to meeting deadlines and ensuring a high-quality design. However, finding shorts in early design cycles can be a time-consuming and resource-intensive task because the design is “dirty” with numerous shorted nets.
To tackle this challenge, designers need a robust LVS solution to address shorts early in the design flow. This article explores common short isolation challenges and presents a novel solution that integrates LVS runs with a powerful debug environment for faster and more efficient verification.
Design size, component density, and advanced nodes like 5 nm and below all contribute to the growing complexity of SoC designs. With layouts containing billions of transistors, connectivity issues like shorted nets can proliferate. Shorts can occur between power/ground networks or signal lines and may result from misalignment, incorrect placement, or simply the close proximity of electrical connections in densely packed areas of the chip.
To read the full article, click here
Related Semiconductor IP
- PUF FPGA-Xilinx Premium with key wrap
- ASIL-B Ready PUF Hardware Premium with key wrap and certification support
- ASIL-B Ready PUF Hardware Base
- PUF Software Premium with key wrap and certification support
- PUF Hardware Premium with key wrap and certification support
Related White Papers
- Reduce SoC verification time through reuse in pre-silicon validation
- Simplifying SoC Verification by communicating between HVL Env and processor
- Creating core independent stimulus in a multi-core SoC verification environment
- Fast, Thorough Verification of Multiprocessor SoC Cache Coherency
Latest White Papers
- e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications
- How to design secure SoCs, Part II: Key Management
- Seven Key Advantages of Implementing eFPGA with Soft IP vs. Hard IP
- Hardware vs. Software Implementation of Warp-Level Features in Vortex RISC-V GPU
- Data Movement Is the Energy Bottleneck of Today’s SoCs