"Early and accurate" power analysis: myth or reality?
By Preeti Gupta, Director RTL Product Management, Apache Design, Inc. (a subsidiary of ANSYS)
EETimes (4/11/2012 6:43 PM EDT)
Power is receiving a mounting share of attention. Innovation, fueled by the information and internet age, poses new challenges for electronic systems across a spectrum of applications. Mobile devices continue to break new frontiers of functional integration. Phones are now your email, social networking interface, video and music player, gaming device, camera, GPS, and more – all rolled into one. Yet the smart phone must survive through the day, and hopefully longer, without having to recharge the battery. Data centers and cloud computing grapple with power and carbon footprints as they move and process incredible amounts of data back and forth, consuming electricity to the order of 1-2% of the total that the entire world consumes. Advances in fabrication technology have made it possible for processors and system-on-chips (SoCs) to boast of over three-billion transistors, also pushing the limits of power density, integrity and reliability.
To read the full article, click here
Related Semiconductor IP
- Root of Trust (RoT)
- Fixed Point Doppler Channel IP core
- Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
- Polyphase Video Scaler
- Compact, low-power, 8bit ADC on GF 22nm FDX
Related White Papers
- Guidelines for early power analysis
- Throttle IP Core Power Dissipation: Use RTL Power Analysis Early and Often
- Power awareness in RTL design analysis
- Reducing power in AMD processor core with RTL clock gating analysis
Latest White Papers
- Reimagining AI Infrastructure: The Power of Converged Back-end Networks
- 40G UCIe IP Advantages for AI Applications
- Recent progress in spin-orbit torque magnetic random-access memory
- What is JESD204C? A quick glance at the standard
- Open-Source Design of Heterogeneous SoCs for AI Acceleration: the PULP Platform Experience