Estimate power at RTL to identify problems early
Aniruddha Gupta & Himani Grover (Freescale)
EDN (August 05, 2015)
SoC power consumption is a key differentiating feature. The initial estimated power of the design is often less than the power use seen on silicon. This happens because there is no power estimation flow available that can accurately correlate power estimation results with the silicon results. Also, for parts that involves a lot of new design features & IP blocks, the exact gate count details are difficult to predict early in the flow.
In addition to more accurate power-estimation flow, there is a need for RTL-stage power estimation, offering the opportunity to reduce power early in the design. This paper discusses the basics of power estimation, and a power-estimation flow at RTL level, which should be known to everyone designing IP & SoCs.
To read the full article, click here
Related Semiconductor IP
- CXL 3 Controller IP
- PCIe GEN6 PHY IP
- FPGA Proven PCIe Gen6 Controller IP
- Real-Time Microcontroller - Ultra-low latency control loops for real-time computing
- AI inference engine for real-time edge intelligence
Related White Papers
- Throttle IP Core Power Dissipation: Use RTL Power Analysis Early and Often
- Static Checks for Power Management at RTL
- Arrgghh! My FPGA's not working: Problems with the RTL
- Power analysis of clock gating at RTL
Latest White Papers
- Adaptable Hardware with Unlimited Flexibility for ASIC & SoC ICs
- CAST Provides a Functional Safety RISC-V Processor IP for Microchip FPGAs
- Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip
- Soft Tiling RISC-V Processor Clusters Speed Design and Reduce Risk
- 8051s in Modern Systems: Interfacing to AMBA Buses