Implementing custom DDR and DDR2 SDRAM external memory interfaces in FPGAs (part 1)

By Danesh Jothiprahasam, Altera Corp.
pldesignline.com (March 17, 2010)

Note

This is a two-part article that focuses on the design guidelines and describes how to implement DDR or DDR2 external memory interfaces (EMIFs) using FPGAs via ALTDLL and ALTDQ_DQS megafunctions. This article does not include information about simulation, timing analysis, and board-level constraints that are used to demonstrate and validate these interfaces. For more information, refer to Application Note AN565.

ALTDLL and ALTDQ_DQS Megafunction Overview

FPGAs referenced in this article have complex dedicated I/O circuitries that are primarily designed to support EMIF. The ALTMEMPHY megafunction is designed to support the most common memory standards, such as the DDR , DDR2 SDRAM, and QDR II+/QDR II SRAM (in a burst length of 4) interfaces. Other external memory standards such as Mobile DDR, QDR II+/QDR II SRAM (in burst length of 2), or customized DDR and DDR 2 SDRAM external memory standards are not supported. Instead, the ALTDLL and ALTDQ_DQS megafunctions are used to access the FPGA architecture and build a custom EMIF.

DDR and DDR2 SDRAM in an FPGA Design Flow

These design guidelines provide the best practices for DDR and DDR2 SDRAM custom memory interface implementation in Stratix III and Stratix IV FPGAs. Figure 1 shows the design flow that is required for the EMIFs for these FPGAs.

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