How to design 65nm FPGA DDR2 memory interfaces for signal integrity
By David Banas, Xilinx
January 24, 2007 -- pldesignline.com
Practical techniques for "correctness by design" in DDR2 interfaces, from a signal integrity (SI) perspective; follow these guidelines to make your next 65nm FPGA design a success.
This article presents practical techniques for incorporating "correctness by design" in DDR2 interfaces, from a Signal Integrity (SI) perspective, using the current generation of available design tools. Some common DDR2 design errors are analyzed, as well as the tradeoffs between some popular design alternatives.
January 24, 2007 -- pldesignline.com
Practical techniques for "correctness by design" in DDR2 interfaces, from a signal integrity (SI) perspective; follow these guidelines to make your next 65nm FPGA design a success.
This article presents practical techniques for incorporating "correctness by design" in DDR2 interfaces, from a Signal Integrity (SI) perspective, using the current generation of available design tools. Some common DDR2 design errors are analyzed, as well as the tradeoffs between some popular design alternatives.
To read the full article, click here
Related Semiconductor IP
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
- Voltage and Temperature Sensor with integrated ADC - GlobalFoundries® 22FDX®
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
Related Articles
- How to Design Secure SoCs: Essential Security Features for Digital Designers
- How to design secure SoCs Part IV: Runtime Integrity Protection
- Meeting signal integrity requirements in FPGAs with high-end memory interfaces
- Memory Design Considerations When Migrating to DDR3 Interfaces from DDR2
Latest Articles
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks
- Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings
- A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
- An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS