How to design 65nm FPGA DDR2 memory interfaces for signal integrity
By David Banas, Xilinx
January 24, 2007 -- pldesignline.com
Practical techniques for "correctness by design" in DDR2 interfaces, from a signal integrity (SI) perspective; follow these guidelines to make your next 65nm FPGA design a success.
January 24, 2007 -- pldesignline.com
Practical techniques for "correctness by design" in DDR2 interfaces, from a signal integrity (SI) perspective; follow these guidelines to make your next 65nm FPGA design a success.
This article presents practical techniques for incorporating "correctness by design" in DDR2 interfaces, from a Signal Integrity (SI) perspective, using the current generation of available design tools. Some common DDR2 design errors are analyzed, as well as the tradeoffs between some popular design alternatives.
To read the full article, click here
Related Semiconductor IP
- xSPI Multiple Bus Memory Controller
- MIPI CSI-2 IP
- PCIe Gen 7 Verification IP
- WIFI 2.4G/5G Low Power Wakeup Radio IP
- Radar IP
Related White Papers
- Meeting signal integrity requirements in FPGAs with high-end memory interfaces
- How to Design Secure SoCs: Essential Security Features for Digital Designers
- Memory Design Considerations When Migrating to DDR3 Interfaces from DDR2
- DDR2 Signal Integrity