Compiler optimization for DSP applications
By Eran Belaish, CEVA
Jul 23 2007 (3:00 AM) -- Embedded.com
As DSP processors become more and more powerful, the portion of code that can remain at the C level increases. However, compilers cannot produce optimized code without assistance from the programmer. To maximize the performance, the programmer must tune the compiler using various compilation options.
Unfortunately, it is quite common to find DSP applications that don't take advantage of the tuning capabilities of the compiler. Instead, they are compiled with the same set of compilation options throughout the whole application. This method ignores the special needs of each function.
Smart selection of compilation options can yield a dramatic code performance improvement. For example, code size can be greatly reduced. This is often a major factor when evaluating the cost of a product, as it has a direct influence on the amount of memory required. This article shows how to improve code size consumption as well as the consumption of other important resources.
To read the full article, click here
Related Semiconductor IP
- NPU IP Core for Mobile
- NPU IP Core for Edge
- Specialized Video Processing NPU IP
- HYPERBUS™ Memory Controller
- AV1 Video Encoder IP
Related White Papers
- Achieving Better Code Optimization in DSP Designs
- How to exploit 17 tried and true DSP power optimization techniques for wireless applications
- DSP optimization strategies using simulators and profilers
- Achieving Optimized DSP Encoding for Video Applications
Latest White Papers
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
- Transition Fixes in 3nm Multi-Voltage SoC Design
- CXL Topology-Aware and Expander-Driven Prefetching: Unlocking SSD Performance
- Breaking the Memory Bandwidth Boundary. GDDR7 IP Design Challenges & Solutions
- Automating NoC Design to Tackle Rising SoC Complexity