Agile Verification for SoC Design

By Paul Cunningham, Cadence Design Systems
EETimes (June 3, 2021)

As agile methods are established to improve productivity and quality, interest is growing in hardware design.

Still, success in the hardware domain is generally perceived to have been limited. Reality is probably somewhat better than perception as some agility trends in hardware are not explicitly labeled as such.

For example, we see increasing efforts to decouple IP-level design and verification from SoC-level design and verification. In that case, each IP team runs asynchronously from SoC projects that operate on a “train model,” picking up whatever version of the IPs ready at the time an SoC design leaves the station.

While not branded as agile, this approach does align with an agile philosophy.

To read the full article, click here