A practical approach to reusing HDL code in FPGA designs

From the very first day that you learn a new hardware description language (HDL), you reuse code. Initially, this might involve copying an example and modifying it in order to learn and expand your knowledge. Later, you start looking for common blocks of code so as not to re-invent the wheel. Alternatively, you could decide to reuse an entire design and recode parts of it to create a variant.

Despite the good efforts of the design community to espouse design-for-reuse as the Holy Grail, what many engineers – including thousands of FPGA designers like you worldwide – do in reality is recycle code. This is no disgrace. Actually, it is very smart. Recycling allows you to quickly fill up those monstrously large FPGAs with blocks of code from previous designs, IP, and your own custom code.

While recycling has its advantages, it is recommended that you follow a solid recipe for success in order to evaluate recycled code before using it within your new project. If you do not follow these simple steps, all the time you thought you would save by recycling the code in your new FPGA could easily be lost trying to get it to work correctly.

This is practical reuse – a working recipe for getting your next design quickly completed by reusing code that already exists at your corporation. And, you will likely find that looking at the problem from a completely different angle will actually lead to more and more reuse in your next projects.

Practical reuse is a discovery process performed with or without tools. This process includes the following steps:

• Determine design integrity: Is the code complete and do you understand (at a high-level) what the code does?
• Determine code quality: Can the code be easily reused and does it meet any standards you might have?
• Establish design validity: Does the design simulate and function as expected?
• Share knowledge: Does everyone in your company have access to the design?

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