What's Changing In SerDes
SerDes is all about pushing data through the smallest number of physical channels. But when it comes to AI, more data needs to be moved, and it has to be moved more quickly.
Todd Bermensolo, product marketing manager at Alphawave Semi, talks with Semiconductor Engineering about the impact of faster data movement on the transmitter (more power) and on the receiver (gain and advanced equalization), how to ensure signal integrity, and tradeoffs involving bandwidth, power, reach, and latency.
Related Semiconductor IP
- SerDes
- Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
- 100G SerDes PAM4 PHY
- 20G MSS (Multi-standard SerDes) PHY
- Multi-Rate Serdes IP Solution
Related Videos
- Scaling Performance In AI Systems
- Cadence’s Silicon Proven UCIe IP in TSMC 3nm
- Livelocks And Deadlocks In NoCs
- Scenario Coverage In Formal Verification
Latest Videos
- How UCIe 3.0 Redefining Chiplet Architecture: From Protocol to Platform
- Teradyne Testimonial: Silicon Creations' 16nm SerDes Enables Fastest TTM and Most Cost-Effective Teradyne ASIC Development To-Date
- Webinar: Unpacking System Performance – Supercharge Your Systems with Lossless Compression IPs
- Arm: From Cloud-to-Car Architecture
- High Performance RISC-V is here!