The SerDes PHY IP meets the requirements of broad range of market segments including network communication, PC interconnect, data storage, enterprise routers, servers, industrial & test equipment, defence and aerospace etc. With seamless interoperability with available controllers it provides unique solution to customer’s system applications.
The vendor offers low power, low latency, integrated clocking and small footprint SerDes Quad PHY IP that supports one, two, four lanes per macro configuration.
| Standards | Data Rate (Gbps) | Organization |
| PCI Express Gen4/3/2/1 | 16/8/5/2.5 | PCI-SIG |
| USB 3.1 Gen2/1 | 10/5 | USB.org |
| SATA Gen 3/2/1 | 6/3/1.5 | SATA |
| 10GBase-KX4 | 3.125 | IEEE |
| 1000Base-KX | 1.25 | IEEE |
| 10GBase-KR / XFI | 10.3125 | IEEE |
| XAUI | 3.125 | IEEE |
| DisplayPort | 8.1 – 1.6 | VESA |
| HSSTP | 12.5 | ARM |
| EPON/GPON/XGPON | 1.25 / 2.488 / 9.95 | IEEE |
| SGMII/QSGMII | 1.25/5.0 | Cisco |