Efficient Scaling of AI Accelerators for Achieving High Performance and Throughput
UALink, the standard for AI accelerator interconnects, facilitates this scalability by providing low-latency, high-bandwidth communication. As a member of the UALink Consortium, Cadence offers verified UALink IP subsystems, including controllers and silicon-proven PHYs, optimized for robust performance in both short and long-reach applications and delivering industry-leading power, performance, and area (PPA).
Unmatched Bandwidth, Ultra-Low Latency, and Power Efficiency for AI Accelerators
- XPU-to-XPU Scale-Up Connectivity — The UALink subsystem IP enables scale-up connectivity for AI systems, supporting the emerging 1.6T and 800G networks
- Integrated Debugging Features — Includes features like Flit-play for debugging or error injection and Flit-capture for field debugging
- Multi-Line Rate Support — Supports 100G and 200G data rates
- FEC Interleave Options — 1-way, 2-way, and 4-way interleaves
- Optional Features — Packet compression, encryption, and security
- Standard Features — Atomic support, multiple VCs, bifurcation, UART buffers, DL layer loopback, DL-FLIT play and capture, transmitter pacing, MSG service, programmable RX credit, authentication tags, latency monitoring, and more
