Xilinx preps 10 million-gate FPGAs

Xilinx preps 10 million-gate FPGAs
By Craig Matsumoto, EE Times
May 22, 2000 (11:38 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000522S0025

SAN JOSE, Calif. — Xilinx Inc. (San Jose, Calif.) this week will disclose details of the FPGA architecture that could be the first to reach 10 million gates, or 500 million transistors. The Virtex-II platform will be the basis for multiple Xilinx product families, the first parts of which are planned to begin shipping before the end of the year.

The parts are being built on 120-nm (0.12-micron) CMOS design rules and have been designed for easy migration to 100-nm processes, Xilinx officials said.

The company's largest FPGAs so far are built on the Virtex architecture, which is expected to grow to 3.2 million gates. The jump to 10 million was caused by the need for on-chip memory for larger designs, particularly in the networking and communications markets that are prime targets for larger FPGAs.

Key to Virtex-II is the release of Alliance Series 3.1i software, which brings ASIC -like features to the FPGA flow. But the Virtex-II also will include hardware changes to accommodate multiple millions of system gates.

Virtex-II devices will sport what Xilinx calls active interconnect, which improves routing flexibility by permitting varying lengths of metal interconnect in a design. This can boost performance by allowing certain traces to run shorter lengths than they otherwise would, said Bruce Weyer, senior director of marketing for high-end FPGAs at Xilinx.

Speeds of the Virtex-II parts will run as high as 200 MHz internally and 800 MHz for I/O, Weyer said.