Xelic Announces SONET/SDH Tributary Payload Processor Core Availability for Integration into ASIC or FPGA Networking Applications
-- Xelic, Inc., a leading provider of Networking Intellectual Property and Engineering Design Services today announced the immediate availability of their SONET/SDH Tributary Payload Processor Core for product integration.
The Xelic SONET/SDH Tributary Payload Processor Core (XCSTPP12) performs tributary pointer processing, aligns outgoing tributaries and provides tributary path overhead error detection and performance monitoring at an STS-12/STM-4 rate. The XCSTPP12 implements the industry standard telecom bus architecture for interfacing of various signaling and data transfers. Tributary payload processing is provided for any legal mix of VT1.5/TU11, VT2/TU12, VT3, VT6/TU2 or TU3 tributaries using STS-1/VC-3 or VC-4 frame formats.
“The XCSTPP12 adds to Xelic’s growing portfolio of networking cores and provides our customers with the ability to achieve a higher level of integration for switching applications at the tributary level.” said Doug Bush, Director of IP Development at Xelic.
Xelic cores are available under flexible licensing terms and come complete with full documentation and a comprehensive suite of self-checking tests. Core customization and integration services are also available.
Xelic is a privately held Networking Intellectual Property provider and Engineering Services Company. Xelic offers standards based IP for SONET/SDH, Digital Wrapper, Generic Framing Procedure, ATM, and Forward Error Correction applications. Xelic’s Engineering Services include Product Definition, ASIC/FPGA Development, System Design, Board Design, Firmware Design, and full turnkey solutions. Xelic was founded in January of 2001 and is based out of Rochester, NY. For more information about Xelic, please visit www.xelic.com.
Xelic and XCSTPP12 are trademarks of Xelic, Inc. All other trade names, trademarks, and registered trademarks are the property of their respective owners.
Related Semiconductor IP
- Root of Trust (RoT)
- Fixed Point Doppler Channel IP core
- Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
- Polyphase Video Scaler
- Compact, low-power, 8bit ADC on GF 22nm FDX
Related News
- Cutting-edge 18-bit 100dB Stereo Audio ADC IP Core proven in 28nm Silicon, Offering Unmatched Audio Signal Processing Capabilities is available for immediate Licensing into Audio Chipsets, Digital Cameras, and Automotive Applications
- Xelic Announces Family of SONET/SDH Transport Processor Cores for Integration into FPGA or ASIC Networking Applications
- Xelic Announces Frame Mapped Generic Framing Procedure Core Availability for Integration into ASIC or FPGA Networking Applications
- PLDA Announces Integration of their PCIe 3.0 Controller IP into Kazan Networks' NVMe Over Fabric Fuji ASIC, Providing a Dramatic Increase in Scalability and Flexibility for Storage Applications
Latest News
- How hardware-assisted verification (HAV) transforms EDA workflows
- BrainChip Provides Low-Power Neuromorphic Processing for Quantum Ventura’s Cyberthreat Intelligence Tool
- Ultra Accelerator Link Consortium (UALink) Welcomes Alibaba, Apple and Synopsys to Board of Directors
- CAST to Enter the Post-Quantum Cryptography Era with New KiviPQC-KEM IP Core
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology