Creonic Adds oFEC Codec IP Core to Portfolio, Expanding High-Speed ​Networking Solutions for ASIC and FPGA

Kaiserslautern -- May 21, 2025 --  Creonic GmbH, a leading provider of ready-to-use IP cores for ASIC and FPGA applications, announces the release of its new oFEC (Open Forward Error Correction) codec IP core. The solution supports next-generation optical and high-speed communication systems and is now available in both ASIC and FPGA configurations.

With a focus on reliability and flexibility, the new oFEC core is designed for ultra-fast data transmission in infrastructure such as hyperscale data centers, high-performance computing, and advanced transport networks. Up to 800 Gbit/s are achieved on cutting-edge ASIC technology nodes. On FPGA the core delivers up to 10 Gbit/s, providing a robust and scalable option for prototyping applications. This addition complements Creonic’s extensive FEC portfolio and enables seamless integration into systems utilizing LDPC-based standards, including 25G/50G Ethernet, 100G/400G/800G links, and emerging optical transport standards.

Designed for low latency and high energy efficiency, the core supports standard compliance and is ready for integration with streaming or frame-based architectures. Creonic provides full technical documentation and engineering support as part of its ISO 9001:2015-certified development process.​