USB 3.2 OTG Controller and PHY IP Cores for ultra-high speed, lossless data and power delivery are available for immediate licensing

December 12, 2022 – T2M^IP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s Silicon Proven and mature USB 3.2 OTG Controller and PHY IP Cores in major Fabs and Nodes as small as 12nm. This USB solution is a cornerstone for data transfer for industrial and consumer applications with an outstanding track record of mass production in a wide range of products.

USB 3.2 OTG Controller and PHY IP transceiver core offers all USB 3.2 OTG, Host and peripheral applications and can be configured to support any combinations of USB 3.2 interface speeds of 20Gbps (dual lane) or 10Gbps. While operating in Device Mode it can be dynamically configured to support configurable number of endpoints, interfaces, and configurations and while operating in host mode, it can optionally be configured to support hubs. The complete solution for USB 3.2 IP cores enables drivers to be reused minimizing software development overheads and associated risks involved with custom bare metal driver solutions.

USB 3.2 OTG Controller IP cores can be configured to support all types of USB transfers - be it Bulk, Interrupt and Isochronous. It has full support for all low power features of the USB Specification supporting Suspend, Remote Wakeup and USB 3.0 and USB 2.0 Link Power Management States. USB 3.2 OTG controller has full support for all USB 2.0 test modes features as well as USB 3.0 compliance and USB 3.0 loopback modes which is required for obtaining USB IF certification. This IP core includes OTG features such as RSP, SRP, HNP and ADP along with software configurable options to turn these on/off features.

USB 3.2 PHY IP Cores is compliant with USB 3.2 and 2.0 electrical specifications and supports both the UTMI+ and PIPE4.0 specifications. It includes high-speed mixed signal circuits to enable Gen2 and Gen1 traffic and is backward compatible to high-speed (480Mbps), full-speed (12Mbps), and low-speed (1.5Mbps) data rates. The Physical layer incorporates an active switch to support bi-directional plug-in and particular functionalities to support the USB Type-C connector. With clock inputs from 25MHz crystal oscillator and external clock sources from the core, it integrates an active switch to support the orientation-less connection with USB Type-C connector and is available in both wire-bond and flip-chip package type.

USB 3.2 OTG Controller & PHY IP cores in 12nm, 28nm and 40nm has been used in semiconductor industry’s Scanners, Digital cameras, Removable media drives, Mass storage devices, Display and docking applications, Cloud computing, Automotive applications, Consumer applications, Smartphones and other industrial uses…

In addition to USB 3.2 Controller & PHY IP Cores, T2M ‘s broad silicon Interface IP Core Portfolio includes HDMI, Display Port, MIPI (CSI, DSI, UniPro, UFS, RFFE, I3C), PCIe, DDR, 1G Ethernet, V-by-One, programmable SerDes, OnFi and many more, available in major Fabs in process geometries as small as 7nm. They can also be ported to other foundries and leading-edge processes nodes on request.

Availability: These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request / MailTo

About T2M: T2M^IP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit: www.t-2-m.com