TSMC Introduces N4X Process
Newest 5nm Enhancement Tailored for High Performance Computing Products
HSINCHU, Taiwan, R.O.C., Dec. 16, 2021 – TSMC (TWSE: 2330, NYSE: TSM) today introduced its N4X process technology, tailored for the demanding workloads of high performance computing (HPC) products. N4X is the first of TSMC’s HPC-focused technology offerings, representing ultimate performance and maximum clock frequencies in the 5-nanometer family. The “X” designation is reserved for TSMC technologies that are developed specifically for HPC products.
Leveraging its experience in 5nm volume production, TSMC further enhanced its technology with features ideal for high performance computing products to create N4X. These features include:
- Device design and structures optimized for high drive current and maximum frequency
- Back-end metal stack optimization for high-performance designs
- Super high density metal-insulator-metal capacitors for robust power delivery under extreme performance loads
These HPC features will enable N4X to offer a performance boost of up to 15% over N5, or up to 4% over the even faster N4P at 1.2 volt. N4X can achieve drive voltages beyond 1.2 volt and deliver additional performance. Customers can also draw on the common design rules of the N5 process to accelerate the development of their N4X products. TSMC expects N4X to enter risk production by the first half of 2023.
“HPC is now TSMC’s fastest-growing business segment and we are proud to introduce N4X, the first in the ‘X’ lineage of our extreme performance semiconductor technologies,” said Dr. Kevin Zhang, senior vice president of Business Development at TSMC. “The demands of the HPC segment are unrelenting, and TSMC has not only tailored our ‘X’ semiconductor technologies to unleash ultimate performance but has also combined it with our 3DFabric™ advanced packaging technologies to offer the best HPC platform.”
TSMC’s HPC platform not only offers performance-optimized silicon with N4X technology, but also provides the greatest design flexibility with its comprehensive 3DFabric™ advanced packaging technologies and a broad design enablement platform with our ecosystem partners through the TSMC Open Innovation Platform®.
For more information on the N4X process, please visit https://performance.tsmc.com
Related Semiconductor IP
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- TSMC CLN5FF GUCIe LP Die-to-Die PHY
- Flipchip 1.8V/3.3V I/O Library with ESD-hardened GPIOs in TSMC 12nm FFC/FFC+
- TSMC CLN3FFP HBM4 PHY
- Wi-Fi 7(be) RF Transceiver IP in TSMC 22nm
Related News
- Sofics releases its ESD technology on TSMC 3nm process
- eMemory's Security-Enhanced OTP Qualifies on TSMC N4P Process, Pushing Forward in High-Performance Leading Technology
- Credo Launches 112G PAM4 SerDes IP for TSMC N3 Process Technology
- Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium
Latest News
- SiMa.ai Raises $85M to Scale Physical AI, Bringing Total Funding to $355M
- Armv9 and CSS Royalties Drive Growth in $1bn Arm Q1 Earnings
- Creonic Releases DVB-S2X Demodulator Version 6.0 with Increased Bitwidth and Annex M Support
- Arm Q1 FYE26 Revenue Exceeds $1 Billion for Second Consecutive Quarter
- 1‑VIA Expands Globally with New India R&D Office in Pune to Accelerate Innovation in Data Center Connectivity