Toshiba taps inSilicon's USB 2.0 core for system-on-chip designs
Toshiba taps inSilicon's USB 2.0 core for system-on-chip designs
By Semiconductor Business News
October 22, 2001 (12:41 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011022S0060
SAN JOSE --Intellectual property design core provider inSilicon Corp. today announced it has licensed its Universal Serial Bus (USB) 2.0 host communications core to Toshiba Corp.'s semiconductor group. Toshiba plans to use the USB 2.0 technology in complex system-on-chip designs. The deal comes after Toshiba's successful implementation of designs using inSilicon's USB 1.1 technology, said Kiyofumi Ochii, general manager of Toshiba's System LSI Design Division. Terms of the licensing pact were not released. The optimized USB 2.0 host technology will enable Toshiba to "reduce development costs and bring their advanced technology products to market sooner," said Barry Hoberman, chief operating officer of San Jose-based inSilicon.
Related Semiconductor IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
- RISC-V Debug & Trace IP
Related News
- System Level Solutions Launches Industry-First USB 20Gbps Device IP Core
- ASMedia Technologies Achieves Industry's First SuperSpeed USB 10 Gbps (USB 3.1 Gen 2) Certified Silicon (PCIe to USB 3.1 Gen 2)
- SilabTech announces the release of its USB 3.1 Gen 2 Compliant 10 Gbps SERDES IP Core
- Corigine Unveils First Certified SuperSpeed+ USB 3.1 Gen 2 IP With M31 28nm PHY
Latest News
- Qualitas Semiconductor Secures Strategic IP Licensing Agreement for MIPI Solutions
- Chinese RISC-V Chipmaker SpacemiT Launches K3 AI CPU, Highlighting the Rise of Open-Source Hardware in Intelligent Computing
- Weebit Nano Q2 FY26 Quarterly Activities Report
- Arasan announces the immediate availability of the industries first xSPI NOR + eMMC NAND Combo PHY IP
- AMIQ EDA Gives AI Agents Access to Essential Design and Verification Data