Toshiba taps inSilicon's USB 2.0 core for system-on-chip designs
Toshiba taps inSilicon's USB 2.0 core for system-on-chip designs
By Semiconductor Business News
October 22, 2001 (12:41 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011022S0060
SAN JOSE --Intellectual property design core provider inSilicon Corp. today announced it has licensed its Universal Serial Bus (USB) 2.0 host communications core to Toshiba Corp.'s semiconductor group. Toshiba plans to use the USB 2.0 technology in complex system-on-chip designs. The deal comes after Toshiba's successful implementation of designs using inSilicon's USB 1.1 technology, said Kiyofumi Ochii, general manager of Toshiba's System LSI Design Division. Terms of the licensing pact were not released. The optimized USB 2.0 host technology will enable Toshiba to "reduce development costs and bring their advanced technology products to market sooner," said Barry Hoberman, chief operating officer of San Jose-based inSilicon.
Related Semiconductor IP
- Multi-channel, multi-rate Ethernet aggregator - 10G to 400G AX (e.g., AI)
- Multi-channel, multi-rate Ethernet aggregator - 10G to 800G DX
- 200G/400G/800G Ethernet PCS/FEC
- 50G/100G MAC/PCS/FEC
- 25G/10G/SGMII/ 1000BASE-X PCS and MAC
Related News
- Introducing the Cutting-Edge USB 3.0/ PCIe 3.0 Combo PHY IP Core in 28HPC+ for High-Performance SoC Designs
- System Level Solutions Launches Industry-First USB 20Gbps Device IP Core
- ASMedia Technologies Achieves Industry's First SuperSpeed USB 10 Gbps (USB 3.1 Gen 2) Certified Silicon (PCIe to USB 3.1 Gen 2)
- SilabTech announces the release of its USB 3.1 Gen 2 Compliant 10 Gbps SERDES IP Core
Latest News
- How CXL 3.1 and PCIe 6.2 are Redefining Compute Efficiency
- Secure-IC at Computex 2025: Enabling Trust in AI, Chiplets, and Quantum-Ready Systems
- Automotive Industry Charts New Course with RISC-V
- Xiphera Partners with Siemens Cre8Ventures to Strengthen Automotive Security and Support EU Chips Act Sovereignty Goals
- NY CREATES and Fraunhofer Institute Announce Joint Development Agreement to Advance Memory Devices at the 300mm Wafer Scale