The European Space Agency and Prosilog collaborate to implement a new system level design methodology

Cergy, France – November 28, 2003 – Prosilog SA, a leading provider of innovative solutions for SoC design and verification, announce that it has been selected by the European Space Agency for the implementation of a complete design flow from SystemC transactional level down to RTL implementation.

"ESA has decided to work with Prosilog to investigate new System On Chip design methodology based on SystemC language says Laurent Hili, VLSI/ASIC Engineer, ESA Microelectronics Section.

The objective of this partnership is also to assess new concepts based on OCP-IP protocol, allowing fast IP integration and reuse. We want to be able to perform architectural trade-offs, try several partitioning approaches between hardware and software, and choose between different memory schemes and bus topologies. The cooperation with Prosilog will allow us to address all those challenging topics."

“We are proud to partner with the European Space Agency and contribute actively to demonstrate the benefit of this methodology, says Philippe Laharrague VP Marketing for Prosilog.

Using our Magillem (R) and Nepsys (R) tools, designers from ESA will benefit from a unique development environment allowing them to rapidly integrate IP blocks, optimise their architecture, and move to the RTL implementation.”

About the European Space Agency
The European Space Agency is Europe's gateway to space. Its mission is to shape the development of Europe's space capability and ensure that investment in space continues to deliver benefits to the people of Europe.

About Prosilog SA
Prosilog SA is developing innovative system level design EDA tools, as well as soft IP cores, which help SoC designers to reduce the cycle time of their product design. Prosilog SA provides solutions aiming at automating some of the design and verification phases of SoC.

Magillem (R) is a graphical platform builder for the creation of SoC. It allows the easy integration of different IP blocks, the automatic generation of the interconnection between the IP's as well as the insertion of verification modules. Included in Magillem(R), is the unique Prosilog's IP Creator, which enables fast generation of a VCI, or OCP interface, making it easy to create a common interface for any IP portfolio.

Nepsys (R), a SystemC-based design environment, enables the development, simulation and verification of complex SoC's, from functional level to RTL. Within the Nepsys (R) environment, are included the Compilers SystemC/HDL and HDL/SystemC, the co-simulation assistant for mixed systems (SystemC, VHDL, Verilog, Spice) and the virtual instruments for functional verification.

For more information, visit www.prosilog.com

Magillem and Nepsys are registered trademarks of Prosilog SA.
All the other trademarks are the property of their respective holders