Temento Systems Joins Synopsys in-Sync Program to Enhance ASIC Prototyping with Hardware Debug

ASIC Prototyping enhanced with on-chip debug and observability

Montbonnot - France - June 30, 2005 – Temento Systems SA a leading supplier of Test Automation (EDTA) solutions, today announced that it has joined the Synopsys in-Sync® program to improve the design flow between Synopsys Design Compiler® FPGA (DC FPGA) Synthesis software, and Temento DiaLite™ On-Chip Instrumentation and Debug Tool.

"We are working with Synopsys to optimize the productivity of our mutual customers," said Patrice Deroux-Dauphin, President & CEO of Temento Systems SA. “Our tool brings a clear added value for Synopsys customers and by integrating with DC FPGA, the ASIC strength solution from Synopsys, we can now offer our mutual customers the ability to insert debug-oriented instruments at the RT level, and then synthesize them together with the rest of their design using either Design Compiler or Design Compiler FPGA (DC FPGA). DiaLite will manage the implemented instruments upon debug time”.

The DiaLite Instrumentation (DLI™) debugging tool enables on-FPGA, SoC and IPs debugging and observability by using embedded instrumentation. It provides a fast and easy instrumentation process flow enabling rapid design verification by keeping the same instrumentation whatever the version of your design. You will save days of debugging work by using specific configurations on your chip, taking advantage of instruments like Traffic analyzer, Pseudo-random generator, Triggers, etc. DLI front-end design uses VHDL or Verilog languages and works together with the Design Compiler and Design Compiler FPGA synthesis tools. For more information, visit http://www.temento.com/solutions/fpga.php

"Temento augments Synopsys’ implementation solutions with real-time (FPGA) hardware debugging and observation," said Karen Bartleson, director of Interoperability at Synopsys, Inc. "Together, Synopsys and Temento will cooperate to provide our mutual customers with the best quality of results in the shortest time possible as they prototype their complex SoCs on FPGAs. We are developing this solution with Temento through our in-Sync program, and are looking forward to a productive relationship with Temento."

About the Synopsys in-Sync Program

Synopsys' in-Sync program establishes relationships with EDA vendors to enable customer design flows to run as smoothly as possible as well as identifies optimal joint flows that maximize the productivity of EDA vendors' mutual customers. In-Sync certifies that the joint flows work and provides support to Synopsys' EDA partners. In-Sync is the primary point of contact for questions and technical information regarding Synopsys joint solutions and EDA tool interoperability. For more information, visit www.synopsys.com/partners/insync.

About Temento Systems

 Temento Systems S.A. provides Electronic Design and Test Automation (EDTA) solutions that enable engineers to test and debug electronic products, including System on Chip (SoC), FPGAs, Boards, Multi-Chips Modules (MCMs) and Systems. Temento Systems offers a broad range of solutions focused on systems design test, starting from the earliest stage of design definition (virtual test), straight through hardware testing (physical test). Temento's solutions are used by product development teams, manufacturing teams, maintenance teams, in major companies, and SME in the semi-conductor, telecommunications, consumer electronics, computer, automotive, and aerospace industries. http://www.temento.com

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