Synopsys co-verification modeler targets PowerQuicc

Synopsys co-verification modeler targets PowerQuicc
By Michael Santarini, EE Times
August 7, 2000 (11:37 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000807S0006

SAN MATEO, Calif. — Synopsys Inc. (Mountain View, Calif.) has announced a hybrid hardware/software modeling solution, called CrossLink 8260, for co-verification and debugging of the Motorola PowerQuicc-II MPC8260 communications system-on-a-chip device.

Geoff Bunza, vice president and general manager for the large technology group at Synopsys, said the Motorola SoC incorporates a PowerPC core as well as a peripheral processor that controls a set of 29 peripherals. Three of those peripherals, according to Bunza, are highly complex channel controllers with programmable protocols to handle various communication channels. Other peripherals in the set include DMA controllers, timers and counters.

"The device is very valuable if you are building communication systems, but to date there hasn't been a simulation and verification model that accounts for the core processor and all these peripherals and that meets the requirements of both hardware and software designers," said Bunza. "With CrossLink 8260, we have a complete solution."

Previously, according to Bunza, 8260 customers either had to rely on software models, which allowed debug visibility but were slow and inaccurate, or they had to create hardware models, which were faster and more accurate but didn't offer visibility for debugging. Some customers also developed prototypes, but those often arrived too late in the process for design debugging, he said.

Synopsys claims CrossLink 8260 will shrink development time by 20 percent.

Limited trade-offs

The solution comprises a model source hardware box, the Eaglei hardware software co-verification tool and the new CrossLink model. Thanks primarily to the CrossLink model, the solution lets hardware and software designers "get their cake and eat it too," Bunza said. "You are not forced into making a trade-off between performance of speed and accuracy of precision."

The solution uses 8260 silicon placed in a hardware modeler. Synopsys disables the PowerPC part of the device and uses the hardware modeler to model the peripherals. The peripheral modeling is then melded with an ISS model of the PowerPC core. The Eaglei software makes it all appear to the designer to be "one library element and one chip" in operation, Bunza said.

He said the solution will yield 100 percent modeling accuracy for all the peripherals on the chip and will provide performance of three orders of magnitude over that of full-functional RTL models. "What the combination gives you is the ability to take that, put it into systems, run code, reset, boot up and run application-level code in conjunction with detailed hardware simulation," said Bunza. "It also gives you full control and full visibility, giving you the ability to debug both on the hardware and software side."

The 8260 is the first model for the CrossLink system, but it can be adapted to model other companies' architectures, he said.

CrossLink ranges in price from $25,000 to $250,000 — depending on the customer's current installation environment.