SOI embedded DRAM running on Freescale 90-nm process

Peter Clarke
(01/27/2005 5:34 PM EST)

  LONDON — Startup Innovative Silicon Inc. (Santa Clara, Calif.) is awaiting the return from a Freescale wafer fab in the United States of a 1-Mbit test chip implemented in a 90-nanometer silicon-on-insulator standard logic process, which should confirm progress made with its single-transistor floating-body DRAM technology.

The technology, discussed in 2001 at technical conferences and other conferences subsequently, has the potential to replace conventional DRAM technology which relies on a single-transistor plus a capacitor and has a bit-cell of twice the size of Innovative's so-called Z-RAM technology.

The Z-RAM (Zero Capacitor RAM) makes use of the so-called floating body (FB) effect that occurs in SOI devices, resulting in a cell structure that is based on a single transistor alone, rather than the combination of a transistor and a capacitor. Z-RAM memory designs have been taped out at 90-nm and the technology is scalable to 22-nm design rules. In addition, unlike other high density memory technologies, Z-RAM technology requires no extra mask steps, or exotic materials, the company said.

Mark-Eric Jones, Innovative's recently appointed chief executive officer, said that the company has decided to pursue embedded memory applications through a licensing business model.

Jones' background is with intellectual property licensing at his own company, MEJ Ltd. later 3Soft Corp., and then with Mentor Graphics Corp. and most recently with Monolithic Systems Technology Inc., a licensor of an embedded DRAM technology, referred to as 1T-SRAM.

"We want to be flexible with licensing so the technology can be used in a large number of places. We will offer technology licenses to other design companies and design groups but always for embedded memory. We could have IDMs as licensees, maybe even foundries," Jones said.

Jones said that as embedded memory occupies at least 70 percent of the die area of today's complex SoCs, the combination of Z-RAM memory and existing SOI processing would produce performance and power-saving benefits.

Jones said that the Z-RAM is not only smaller but is also more scalable than alternative DRAM and SRAM technologies and would meet embedded memory requirements of chip designers for the next 15 years. Jones added that a Z-RAM memory cell had been built using FinFET technology.

As the planar technology, at 4F2, has half the bit cell size of conventional DRAM the technology would also be suitable for displacing DRAM technology in standard products.

"Yes, it could do commodity parts. But, mainly for business reasons, we're not going there, initially. There's a high barrier to entry in commodity parts."

Innovative Silicon has been building up a body of experience and patent coverage over the last three years. Although Freescale's 90-nm process is one of the most advanced process yet used, the Z-RAM has been made in different configurations and test circuits in nine wafer fabs to date, according to Pierre Fazan, founder and chief technology officer.

Innovative Silicon has pursued both high-performance and low-power consumption variants of the technology and has five patents granted and 20 patents filed, Jones said.

"In terms of the high-performance approach, we are aware others have worked on similar things. But we are not aware of anyone working on the low power approach," said Jones. "It is likely they would cross one of our patents."

Innovative, which was founded in Lausanne, Switzerland, retains its engineering base there as a wholly-owned subsidiary of a U.S. parent in Santa Clara, California. The company was included in both the first and second iteration of the Silicon Strategies' 60 Emerging Startups list.