SiByte net processor shoots for control

SiByte net processor shoots for control
By Linley Gwennap, EE Times
October 9, 2000 (9:43 a.m. EST)
URL: http://www.eetimes.com/story/OEG20001009S0009

SAN JOSE, Calif. — SiByte Inc. will disclose plans for its first product — a processor for networking — this week at the Microprocessor Forum. Unlike the slew of network processors aimed at accelerating data-plane operations, SiByte's chip, the first in its planned Mercurian family, will typically handle control functions or a mix of the two.

The Mercurian SB-1250 combines two powerful but general-purpose MIPS cores with a set of network interfaces. Power consumption is less than 10 W. SiByte (Santa Clara, Calif.) is nearing tape-out on the processor, with samples planned for the first quarter of next year and product in the second half.

The 1250 can be used in a variety of networking applications, but its general-purpose processors are best suited to the control-plane code. That code is invoked for special-case or exception packets that cannot be handled by the data plane, which is typically im plemented in a set of ASICs or in a network processor, such as Motorola's C-5.

In most networking apps, the control-plane code is far more complicated than the data-plane code and thus is written in a high-level language. As a MIPS processor, the 1250 is compatible with the broad range of compilers and development tools for that architecture, easing software development. In fact, Cisco Systems Inc.'s control-plane code, known as IOS, runs mainly on MIPS today. (Not coincidentally, Cisco is a key investor in the privately held SiByte, as is Juniper Networks.)

QED's RM7000 is commonly used for control-plane processing today. But that part is expected to top out at 500 MHz next year, whereas the SiByte chip will offer two CPU cores at up to 1 GHz each. That may seem like overkill, but performance requirements for the control processor are rising quickly. An OC-192 router, for example, requires four times more performance than an OC-48 router in both the control and data planes.

Indeed, control-plane requirements may be rising faster. With the complexity of such new schemes as the Resource Reservation Protocol (RSVP) and Internet Protocol security (IPsec), more packets are being kicked out of the data plane for handling by the control processor. Combine that with the rapid rise in raw wire speed, and the need for a chip like SiByte's becomes evident.

In some applications, the 1250 can also handle a portion of the data plane, sharing the work with ASICs or coprocessors. In a world where new protocols appear regularly, the 1250 offers the advantage of programmability. Fixed portions of the process, however, can be carved into ASICs.

A less effective use for the 1250 is as a data-plane processor. In that configuration, an 800-MHz 1250 can process 7.2 million packets/second, enough for an OC-48 connection. But the SiByte core is not optimized for packet processing. For pure data-plane code, it will likely be outperformed by other NPUs that cost less.

Code combination

A better appl ication for the 1250 is to combine the control- and data-plane code on one processor. The technique could be used in a highly featured line card, or the 1250 could be the main processor in a customer-premises equipment (CPE) device connecting a midsized office to a WAN. In those cases, the integrated network interfaces simplify the system design.

The SB-1250 is the first product using the company's SB-1 core, disclosed in June. The general-purpose core implements the MIPS64 instruction set, allowing the use of standard compilers and tools.

The company did not include networking-specific optimizations, which could have increased packet-processing performance but broken compatibility with existing tools. For example, the SB-1 is not multithreaded, as are more specialized data-plane processors. Although it supports rarely used floating-point instructions, the core has no bit-manipulation or other instruction extensions for packet processing. Future parts may include such extensions.

The SB-1 executes up to four instructions per cycle at clock speeds of up to 1 GHz but requires only 2.5 W and consumes about 25 mm squared in a 0.15-micron process.

The 1250 combines two of these cores, generating a claimed total of 4,400 Dhrystone MIPS — six times the performance of a 500-MHz QED RM7000, which has only a single dual-issue CPU. QED, now part of PMC-Sierra, plans to release a higher-performance core, code-named Apollo, sometime next year.

An extensive set of logic complements the dual CPUs in the SB-1250. The chip includes a 512k cache that backs the dual 32k caches in each core. The cache connects to the cores using the wide ZBbus, which can transfer an entire 32-byte cache line in one cycle.

Caches often get in the way when handling streaming network data, but the MIPS64 instruction set includes special load instructions that bypass the cache. The cache is useful for holding frequently used route-table entries.

The 1250 also all ows 128k sections of the cache to be partitioned as on-chip SRAM, which can be controlled directly by software. That memory can be used to lock down important data or to queue packets.

The processor supplies two 64-bit double-data-rate SDRAM channels that deliver 4.2 Gbytes/s of peak bandwidth using DDR-266 memory. The interfaces support future SDRAM at up to 400 MHz, providing room for growth.

Comm features

The chip includes three Gigabit Ethernet media-access controllers, connecting directly to external PHY chips for up to 6 Gbits/s of traffic. For Sonet applications, the MACs can be bypassed and a simple ASIC or FPGA interfaced to standard Sonet framers. In that mode, the 1250 supports a single full-duplex OC-48 channel or four OC-12s.

Along with a standard PCI bus, the 1250 includes an LDT interface licensed from Advanced Micro Devices. With a bandwidth of up to 6.4 Gbits/s in each direction, the point-to-point bus can connect to multiple PCI bridges, MACs, ASICs or another SB- 1250.

QED, IBM, Intel and others are building RISC processors that deliver 1,000 Dhrystone Mips or better, but that is just half the performance of one of the SB-1250's two cores. QED plans to double up its Apollo core, but even that device is still likely to trail SiByte's in performance.

In some applications, the 1250 can be used for data-plane and other special-purpose code, but for pure packet processing, a network processor is a better solution. SiByte may adapt its core for that task in the future.

The strength of the 1250 is on general-purpose code. Assuming SiByte can deliver its chip at a reasonable price, it should fare well for networking control code.

Linley Gwennap, co-author of A Guide to Net Processors, is principal analyst of the Linley Group.

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