Sagantec Automates Toshiba Semiconductor Full-Custom Process Migration
Sagantec Automates Toshiba Semiconductor Full-Custom Process Migration
FREMONT, Calif.--(BUSINESS WIRE)--Sept. 10, 2001--Sagantec announced today that Toshiba Corporation's Memory Division (Japan) has adopted Sagantec SiClone for full-custom physical design. Already used by Toshiba's DRAM group in several full-custom designs, SiClone has helped Toshiba physical-design engineers achieve a 6x reduction in design time and 15x reduction in design effort. Toshiba's Memory Division has signed a contract for an undisclosed number of SiClone licenses.
Toshiba's Memory Division is currently using SiClone on its control and interface circuits. Because DRAM control and interface circuits are large custom circuits that comprise both digital and analog functions, they are carefully designed manually. The design time can take many months. In previous technologies (0.25 micron and above), designers used to shrink layout and manually fix design rule errors. However in deep submicron (smaller than 0.18 micron) processes, the technology design rules change dramatically and the shrink path no longer works. Without a tool such as SiClone, designers would have to manually redesign the circuit. Among other designs, Toshiba has used SiClone for their flagship SDRAM, which was re-implemented in the latest technology by using a 0.18 micron design source.
``The ability to quickly introduce designs in the latest technology available has always been a key element in our competitive strategy,'' said Kiminobu Suzuki, Toshiba Chief Specialist. ``However, re-implementation of full-custom memory designs in new process technologies has traditionally been slow and manual. To combat the problem, Sagantec's SiClone has automated the process to deliver results of handcrafted quality in a fraction of the time required with earlier methods. Adopting SiClone provides us with a tremendous competitive advantage with a significant reduction in time to market.''
``Industry leaders such as Toshiba need the best tools and technology to make full use of their competitive advantage in advanced process technologies,'' said Hein van der Wildt, president and CEO of Sagantec. ``We are very proud that Toshiba chose Sagantec SiClone to help its engineers save time and effort for full-custom design work.''
``The semiconductor memory business represents about a quarter of the entire semiconductor market, but the design and implementation of these chips has, until now, relied solely on manual design methodologies,'' van der Wildt continued. ``With SiClone, companies such as Toshiba can accelerate physical design time and in turn speed their time to market. In addition, engineers are able to design in parallel with process development so that as the design rules become fully stable, the physical design can literally be ready in a couple of days,'' van der Wildt concluded.
About SiClone
Released earlier this year, SiClone provides a solution to automate custom physical design re-implementation, process migration and design closure. By automating traditionally manual migration and optimization tasks, SiClone helps companies take advantage of the latest process technology. SiClone targets full custom physical designs such as high performance CPUs and DSPs, memories and analog/mixed-signal circuits. SiClone's ability to handle and preserve the entire design hierarchy lets companies integrate automated physical-design migration and optimization in existing flows. Through SiClone, companies can migrate their designs to denser processes and smaller die sizes -- achieving higher product margins with products brought to market more quickly.
About Sagantec
Sagantec provides software, methodologies and services that enable rapid implementation, reuse and design closure for full custom physical designs in sub-wavelength technologies. The company is working closely with its semiconductor partners and customers to ensure that its products work with the most aggressive technologies of 0.13 micron and below. Sagantec products are specifically designed to accelerate the physical design process of high performance/low power CPUs, and DSPs, dedicated and embedded memories, and analog/mixed-signal circuits. Privately held and funded, Sagantec was founded in 1993 in Israel. Its corporate headquarters is located at 46485 Landing Parkway, Fremont, Calif. 94538. Telephone: 510/360-5200. Facsimile: 510/360-5255. On the web at: http://www.sagantec.com.
Note to Editors: Sagantec acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
Contact:
Sagantec North America, Fremont
Coby Zelnik, 510/360-5200 ext. 110
coby@sagantec.com
http://www.sagantec.com
or
Lee Public Relations
Pam Wasserman, 650/363-0142
pam@leepr.com
Related Semiconductor IP
- RISC-V CPU IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
Related News
- Cadence Custom Design Migration Flow Accelerates Adoption of TSMC N3E and N2 Process Technologies
- Sagantec announces a new migration and DRC correction tool for 28nm and 20nm
- Toshiba Announces Immediate IP Subsystem Availability of PCI Express and DDR3 for Custom LSI Platforms
- Toshiba's "Easy Prototyping" Solution for Custom SoC Development Platform Reduces Need for Customer's Own Design Resources
Latest News
- HPC customer engages Sondrel for high end chip design
- PCI-SIG’s Al Yanes on PCIe 7.0, HPC, and the Future of Interconnects
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- Cadence Unveils Arm-Based System Chiplet
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers