Safety Without Security Is an Illusion in the Age of Autonomous Vehicles
The safety/security equation has changed, and in the era of autonomous, connected vehicles, trust must be engineered from silicon to cloud to ensure true resilience against both malfunction and malicious attack.
By Hassan Triqui, Secure IC
EETimes Europe | June 13, 2025
As the automotive industry pushes toward Level 4 and Level 5 autonomy, the convergence of functional safety and cybersecurity is no longer theoretical; it is operational. A malfunction may cause damage; a cyberattack may cause disaster. The two domains are now inextricably linked. There is no safety without security.
This new reality demands a fundamental redesign of the automotive value chain. Safety-critical systems cannot rely solely on isolated certifications or static design milestones. Security must be integrated from the chip level to the cloud—from the individual electronic control unit to the fleet level—because autonomous vehicles are not standalone machines; they are nodes in a hyperconnected, evolving ecosystem.
Trust must begin at the silicon level
Autonomous vehicles are effectively rolling data centers with real-time mission-critical functions. To ensure their integrity, hardware-based roots of trust must anchor the entire system. These hardware enclaves provide the foundational assurance needed to secure boot sequences, cryptographic operations, and isolation of sensitive processes.
As system architectures grow more complex, many next-generation automotive SoCs are adopting chiplet-based designs, bringing together modular silicon components within a single package. This evolution introduces new security requirements: Each chiplet must be individually authenticated during system boot and must maintain secure, verified communication with neighboring chiplets. Ensuring a trusted chain of custody among chiplets is essential to preserving end-to-end system integrity, especially in safety-critical domains such as braking, steering, or autonomous navigation.
To read the full article, click here
Related Semiconductor IP
- RVA23, Multi-cluster, Hypervisor and Android
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- NPU IP Core for Mobile
- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
- H.264 Decoder
Related News
- Imagination launches the MIPS I6500-F, CPU IP designed for safety-critical systems in an autonomous age
- Arbe Robotics Selects Synopsys' IP to Enable its High-Resolution Imaging Radar to Achieve the Highest Automotive Safety Level for Autonomous Vehicles
- Mentor introduces Tessent Safety ecosystem to meet IC test requirements of the autonomous vehicles era
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
Latest News
- Safety Without Security Is an Illusion in the Age of Autonomous Vehicles
- M31 Ranked in the Top 5% of TPEx-Listed Companies in the Corporate Governance Evaluation for Four Consecutive Years
- SmartDV Introduces Advanced H.264 and H.265 Video Encoder and Decoder IP
- Volantis Unveils Photonic Compute Platform for the AI Era; Raises $9M in Seed Round With Alex Wang, Trevor Blackwell, and Others
- MIPS and Cyient Semiconductor collaborate to bring Custom RISC-V-based intelligent power solutions to AI Power Delivery, Industrial Robotics, and Automotive