Agnisys Offers Free Register Generator for UVM

SAN JOSE, Calif.--February 29, 2012--Agnisys today announced a free version of its Hardware Specification tool – IDesignSpec™. It enables users to capture hardware specification that is automatically converted into implementation code. The free version of IDesignSpec™ is capable of generating complete UVM based register models that can be easily used to verify registers.

“Attending the first day at the DVCon conference and meeting UVM users, it is clear that the user community is asking for a Register Generator that will enable them to quickly use the UVM based verification flow for registers … something that is out of scope for the UVM register package. We are happy to fill that gap with a free version of IDesignSpec™ - an industry first” said Anupam Bakshi, CEO at Agnisys.

“You don’t want to create UVM register models by hand as it will be tedious and highly error prone. With IDesignSpec™ you can simply create the register specification in Word, Excel or OpenOffice, press a button or enter a command and get any output including UVM…” clarified Anupam.

The tool is available for download from the company website http://agnisys.com. It has complete UVM register model generation capability for smaller register/memory maps which will enable people to start using UVM register package immediately.

The UVM generation capability for IDesignSpec™ includes advanced concepts like ability to specify and control coverage, randomizations, constraints, hdl_paths etc. with different scope rules.

IDesignSpec™ enables design verification engineers to describe hardware specification using simple Word/Excel templates and generate a variety of code from it including UVM, OVM, VMM, IP-XACT, SystemRDL, Synthesizable Verilog & VHDL, a variety of documentation including HTML, PDF, SVG etc. and C++ class/header files for Firmware and Software development. Several formats can be imported and a Tcl API is provided for custom output generation.

About Agnisys

Agnisys is a pioneer in creating tools for High Efficiency Design Verification. IDesignSpecTM automates creation of register and memory maps guaranteeing higher quality and consistent results across hardware and software team members. IVerifySpecTM is a solution for verification planning and audits that exposes verification holes driving faster verification closure and achieving code coverage for VLSI and FPGA design projects that span multiple teams and disciplines. For more information, visit www.agnisys.com or follow @Agnisys on Twitter.

About DVCon

DVCon is the premier conference for discussion of the functional design and verification of electronic systems.