Rambus Showcases Industry's First TSMC 90 Nanometer Serial Link Cell Solution at DesignCon 2004
DESIGNCON WEST, SANTA CLARA,CA - February 04, 2004
- Rambus Inc. (NASDAQ: RMBS), a leading developer of chip-to-chip interface products and services, today announced that it is showing the industry's first serial link cell developed on TSMC's 90 nanometer (nm) process technology. This 90nm cell is being featured in a first-of-its-kind, live demonstration in the Rambus booth (#311) at DesignCon West located at the Santa Clara Convention Center in Santa Clara, California through February 5, 2004. The demonstration features a Rambus RaSer(tm) PHY serial I/O solution providing 10Gbps aggregate bandwidth with a quad XAUI cell. As a cost-effective, highly integrated solution suitable for very high channel count application specific integrated circuit (ASIC) or application specific standard product (ASSP) designs, this breakthrough provides the necessary, intensive bandwidth levels that ensure the future deployment of various interface standards, including 10-Gigabit Ethernet XAUI, as well as high-speed backplane applications.
The live demonstration features a Rambus RaSer cell for XAUI and turbo 4Gbps XAUI applications running on 90nm process technology and simulates real backplane traffic by operating at 3.125Gbps per lane over 40 inches on a common FR4 copper backplane. The superior jitter performance and extremely low power consumption (71 mW per full duplex channel) of this cell provides designers a solution that meets the stringent requirements of system backplanes pushing through large amounts of data in Ethernet switches, routers, multi-service edge switches/routers, telecom platforms and wireless networks infrastructure.
"Developing our RaSer PHY serial link technology on 90 nanometers provides our customers with a denser and highly integrated solution for bandwidth-intensive networking systems," said Jean-Marc Patenaude, marketing director for the Logic Interface Division at Rambus. "Our solution is one of the most advanced technologies for enabling increased bandwidth at a reduced cost and smaller form factor, thereby enabling end customers with faster, smaller and higher density systems by integrating a large number of channels on a single chip."
The RaSer(tm) Family of Serial Link Cells
The Rambus family of RaSer cells is available in a wide variety of processes, including TSMC 0.18µm, 0.13µm, and 90nm as well as UMC 0.18µm and 0.13µm. The family offers designers a scalable serial link architecture that addresses current and future serial link applications requiring the highest bandwidth and channel count on a single chip. The RaSer serial link technology can be employed across a variety of different networking applications, including switch and router backplanes, Gigabit and 10-Gigabit Ethernet, PCI Express, Fibre Channel, and fiber optic network interfaces and any other custom chip-to-chip applications.
The Rambus RaSer family of serial link cells is offered as an analog core library cell, for ASIC and ASSP designs. Offering a complete serial link solution, the RaSer cells contain serializer, transmitter, receiver, deserializer, clock multiplier and clock recovery circuitry. These cells are designed to meet the physical layer requirements for a wide range of serial link applications, each of which may have different logical requirements (protocol, framing, coding, etc.). As a replacement to stand-alone discrete serial link components, the RaSer family may be integrated with other communications functions in order to offer better integration and reduced component count.
About Rambus Inc.
Rambus is one of the world's leading providers of chip-to-chip interface products and services. The company's breakthrough technology and engineering expertise have helped leading chip and system companies to solve their challenging I/O problems and bring industry-leading products to market. Rambus's interface solutions can be found in numerous computing, consumer electronic and networking products. Additional information is available at www.rambus.com.
Rambus is a registered trademark of Rambus Inc. and RaSer is a trademark of Rambus Inc. Other trademarks that may be mentioned in this release are the intellectual property of their respective owners.
Related Semiconductor IP
- RISC-V CPU IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
Related News
- Agere Systems Announces Comprehensive 90 Nanometer Custom Chip Platform Targeted for Communications Applications
- Agere Systems Demonstrates Fastest SerDes Circuitry Utilizing 90 Nanometer Low-K Technology
- UMC and AMIC Technology Announce Production of 90 Nanometer 36Mb High Speed ZeBLTM SRAM Family
- Artisan Showcases Comprehensive Analog and Digital IP Solutions for Nanometer Design at 2004 Design Automation Conference
Latest News
- HPC customer engages Sondrel for high end chip design
- PCI-SIG’s Al Yanes on PCIe 7.0, HPC, and the Future of Interconnects
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- Cadence Unveils Arm-Based System Chiplet
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers