Program draws IP cores into IBM's design flow

Program draws IP cores into IBM's design flow
By Anthony Cataldo, EE Times
March 9, 2002 (10:37 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020307S0032

SAN MATEO, Calif. — IBM Microelectronics has kicked off a program intended to make sure that intellectual property (IP) cores from third parties work properly with IBM's proprietary design tools when designed into an IBM ASIC.

IBM's Blue Logic IP Collaboration Program formalizes an effort to have IP cores interoperate with other cores on a device and be brought into an ASIC design flow without breaking IBM's tools.

ASIC makers have argued for years that too much attention has been focused on standardizing IP for reuse and not enough on methodology, said Mark Weir, manager of strategic investments for IBM Microelectronics in Burlington, Vt. "Our customers will have a much greater success with IP that is tailored to our methodology. It's a more meaningful way to standardize."

Tensilica Inc.'s Xtensa configurable processor will be the first core to have hooks to IBM's design methodology. Specifically, the Xtensa core has be en tailored for IBM's proprietary timing and test tools.

"Some of the restrictions that a design has to meet with our tools are related to the specifics of how the clocks and feedback paths are implemented in a design to ensure that they will work smoothly with our ASIC flow," Weir said.

IBM chose Tensilica as its first "platinum" IP supplier because the Xtensa core is being used in ASICs now shipping in production quantities. Tensilica has had "significant success with some existing IBM ASIC customers and they appear to have a selection of IP that will continue to be of interest to our customers in the future," Weir said.

Tensilica's configurable processor core will not affect IBM's plans to offer other embedded processors, such as PowerPC and ARM. The company is also looking to add more DSP cores to the program, Weir said. Today IBM offers the ZSP core licensed from LSI Logic Corp.

Picky partner

For IP suppliers, becoming part of IBM's collaboration progra m will likely be viewed as a valuable cachet that would help set them apart from those struggling for legitimacy. IBM is the leading ASIC supplier, and is known for being selective about the companies for which it chooses to build devices.

Similarly, IBM intends to be choosy about its IP partners. Weir said IBM is interested in "credible suppliers," which includes those that have already been vetted within the company's Microelectronics group, are likely to be in business for the long-term and have preverified cores.

By year's end IBM should have 20 or so companies in the IP collaboration program, which is just a fraction of the 200 suppliers who have licensed the company's CoreConnect on-chip bus. Weir said CoreConnect licensees won't necessarily be given preferential treatment when being considered for the program.

The IP program is not intended to supplant IBM's internal efforts to develop IP or license cores from third parties. Under the IP collaboration program, IBM's ASIC custom ers will have to obtain licenses directly from the IP vendors.

"We develop and license IP but we still don't have and never will have every block that every customer will ever want," Weir said. "This program is an effort to expand the range of IP that is ready to be integrated into IBM's ASICs."