PLX to detail BulletTrain on-chip architecture

PLX to detail BulletTrain on-chip architecture
By Loring Wirbel, EE Times
January 15, 2003 (10:06 a.m. EST)
URL: http://www.eetimes.com/story/OEG20030115S0015

SAN JOSE, Calif. — PLX Technology Inc. will disclose architectural details next week of a generic on-chip fabric architecture called BulletTrain, which represents the company's bid to offer interconnect products that meet the PCI Express Base specification and PCI Express Advanced Switching specification.

At the Bus and Board Conference, which begins Jan. 20 in Long Beach, Calif., PLX will explain how the core SwitchYard fabric at the heart of its BulletTrain architecture can be linked to expandable ingress and egress ports, making it easier to broaden applications than with variable-sized buffers.

Each port that connects to a specific I/O layer is defined by what PLX calls "Station IP," which refers to generic intellectual property rather than Internet Protocol links. If a company has its own IP cores, PLX allows them to link to BulletTrain through software "gaskets" defined through application programming interfaces. Product ma nager Danny Chi said that defining a rule-based architecture appropriate for any PCI Express implementation eliminated the need for different switches and protocol bridges for different designs. The SwitchYard fabric is a point-to-point mesh that can expand in multiple dimensions, and the BulletTrain topology with SwitchYard at its center can be used with alternative interconnects such as HyperTransport.

The only thing that changes with more ingress and egress points is the number of packet queues, Chi said. Since the fabric is intelligent, no processor interdiction from the control plane is required. PLX will offer its first PCI Express base chips utilizing BulletTrain in the second half of 2003, followed by PCI Express Advanced Switching chips in early 2004.