PLDA Announces the Industry's First True Look at PCIe Gen 2
Company Unveils Plans for Breakthrough Demo of PCIe Gen 2 During DAC
SAN JOSE, Calif. -- May 28, 2007 -- PLDA, the industry leader in the high-speed bus IP market, today announced that it will be demonstrating a complete PCIe Gen 2 solution at the Design Automation Conference (DAC) June 4-7 in San Diego, CA, USA..
The PLDA PCIe Gen 2 demo will include a FPGA-based board running PLDA’s PCIe Gen 2 XpressRich IP on a server Platform featuring two quad processors from the industry leading processor manufacturer. This PCIe Gen 2 demo will provide the best look to date at actual throughput numbers – an industry first.
“There have been previous demos of PCIe Gen 2, however they were not equipped to effectively showcase a real life situation,” stated Stephane Hauradou, PLDA’s CTO. “By partnering with a leader who is helping create the future of PCIe, PLDA can effectively demonstrate PCIe Gen 2 as a user might truly experience it.”
About the PLDA PCIe Gen 2 Demo
The PLDA demo is slated for June 4 and 5 during the 44th Design Automation Conference (DAC) in San Diego, CA. Because it will require disclosure of confidential information, qualified engineering managers designing ASICs with PCIe 2.0 interface should register before June 1st in order to receive and return an NDA. The demonstration will take place at the San Diego Convention Center. To request a demo appointment, please contact PLDA.
About PLDA
PLDA designs and sells a wide range of ASIC and FPGA interfacing solutions for the PCI Express, PCI-X, PCI and derivative protocols. The company offers complete solutions, including IP cores, hardware, software, consulting services, and comprehensive technical support provided directly by the IP designers.
Founded in 1996 and profitable since its inception, PLDA is privately owned. The company maintains offices in California and France, and has a strong international Distributor's network. For additional information about PLDA, please visit http://www.plda.com.
Related Semiconductor IP
- PCI Express PHY
- Multi-Channel Flex DMA IP Core for PCI Express
- PCIe - PCI Express Controller
- PCI Express PIPE PHY Transceiver
- Scalable Switch Intel® FPGA IP for PCI Express
Related News
- PLDA and OmniPhy Announce PCIe Gen 2 Controller and PHY Combination for the TSMC 28nm Process
- LogicVision's Embedded SerDes Test Selected by PLX Technology for Gen 2 PCI Express Device Family
- ASIC Architect Announces the Availability of PCI Express Gen 2 Controller Cores
- PLDA Announces Immediate Availability of PCIe Gen 2 FPGA IP Design for Altera's Stratix II GX
Latest News
- Qualitas Semiconductor Demonstrates Live of PCIe Gen 6.0 PHY and UCIe v2.0 Solutions at ICCAD 2025
- WAVE-N v2: Chips&Media’s Custom NPU Retains 16-bit FP for Superior Efficiency at High TOPS
- Quintauris releases RT-Europa, the first RISC-V Real-Time Platform for Automotive
- PQShield's PQCryptoLib-Core v1.0.2 Achieves CAVP Certification for a broad set of classical and post-quantum algorithms
- M31 Debuts at ICCAD 2025, Empowering the Next Generation of AI Chips with High-Performance, Low-Power IP