ASIC Architect Announces the Availability of PCI Express Gen 2 Controller Cores
ASIC Architect strengthens its position in high-speed interconnect market.
Santa Clara, CA -- Jan. 22, 2008 -- ASIC Architect, Inc. today announced the availability of PCI Express Gen 2 Controller Cores - in multiple lane width configurations - x16, x8, x4, x1. This follows the footsteps of company's highly successful industry-leading PCI Express Gen 1 Controller Cores. The product is developed based on PCI Express Specification 2.0 and is backward compatible with PCI Express Specification 1.1.
ASIC Architect is a high-speed controller solutions company. The company's portfolio of high end products includes PCI Express, DDR and SATA controller cores. The cores provide logic solution targeted for wireless, handheld, consumer, telecommunication and networking markets. With the release of PCIe Gen 2 Controller Core in multiple lane configurations ranging from x16 down to x1, the company is poised to enter into very high-end bandwidth-starving markets.
"With the latest PCIe Gen2 standard, compliance and cross mode interoperability testings are pushed to new and higher levels. ASIC Architect's solutions are based on a commitment to rigorous simulation-based and hardware-based compliance validation that translates into higher confidence for their customers" said Chris Browy, Vice President of Sales and Marketing, Avery Design Systems, "Through a close partnership and driven by ASIC Architect's high quality standards Avery can supply our Gen2 VIP with the most robust compliance test suites and BFMs for simulation-based compliance testing."
"ASIC Architect is an industry leader in providing solutions in the areas of high-speed interconnect and mass storage ASIC/SoCs. The PCIe Gen2 Controller Cores are the newest addition to our strong product portfolio. The add-on bridge products - AMBA® 2 AHBTM Bridge, AMBA 3 AXITM Bridge results in an end-to-end solution to connect PCI Express to AMBA," says Kishore Mishra, president and CEO of ASIC Architect. "The PCIe Gen2 Controllers have been architected to meet the stringent power, latency, and gate-count numbers of the next generation ASIC/SoC in storage, communication, networking and consumer markets."
About ASIC Architect Products and Services:
ASIC Architect offers a wide range of high speed controller cores - PCI Express, DDR and SATA Cores, and the solution logic for these high-end cores for ASIC/SoC. The company is headquartered at Santa Clara, CA with an international presence at Bhubaneswar, India.
About Avery Design Products and Services:
Avery Design Systems Inc. is a supplier of functional verification products and service that enables dramatic productivity improvements of the ASIC-based systems and SOC verification process. Additional information about Avery Design Systems is available at http://www.avery-design.com.
Related Semiconductor IP
- 200G/400G/800G Ethernet PCS/FEC
- 50G/100G MAC/PCS/FEC
- 25G/10G/SGMII/ 1000BASE-X PCS and MAC
- Multi-channel, multi-rate Ethernet aggregator - 10G to 400G ZX (e.g., Telecom)
- Multi-channel, multi-rate Ethernet aggregator - 10G to 100G ZX (e.g., Telecom)
Related News
- PLDA and GUC Delivers Fully Integrated PCI Express Gen 4 Solution for TSMC's 16nm FinFET Plus Process
- Accelerate Innovation: Harnessing the Speed of Tomorrow with PCIe Gen 4 PHY and Controller IP Cores
- LogicVision's Embedded SerDes Test Selected by PLX Technology for Gen 2 PCI Express Device Family
- PLDA Announces Immediate Availability of PCIe Gen 2 FPGA IP Design for Altera's Stratix II GX
Latest News
- How CXL 3.1 and PCIe 6.2 are Redefining Compute Efficiency
- Secure-IC at Computex 2025: Enabling Trust in AI, Chiplets, and Quantum-Ready Systems
- Automotive Industry Charts New Course with RISC-V
- Xiphera Partners with Siemens Cre8Ventures to Strengthen Automotive Security and Support EU Chips Act Sovereignty Goals
- NY CREATES and Fraunhofer Institute Announce Joint Development Agreement to Advance Memory Devices at the 300mm Wafer Scale