Philips starts 65-, 90-nm chip design in India

K.C. Krishnadas
(06/30/2005 6:47 AM EDT)

  BANGALORE, India — European consumer electronics giant Royal Philips Electronics said Thursday (June 30) it is starting work on 65- and 90-nanometer chip design at its development center here. The work is aimed at the next-generation of consumer chips including those based on its Nexperia platforms.

"The next-generation consumer platform chip will enable new applications for our next-generation consumer platform such as high-definition motion-based enhancements and three-dimensional TVs," said Rene Penning de Vries, chief technology officer at Philips Semiconductors. The chip will include multiple MIPS and Trimedia digital signal processors and various application specific IP blocks designed using Philips' 65-nm process, he added.

Tapeout is expected next year, and designers here will work with Philips' centers in San Jose, Calif., and Philips Research in Eindhoven, Netherlands, on the new chip.

"Such work will take this center to a new, high level of design complexity," said Rajeev Mehtani, director, Philips Semiconductors, based here.

Another initiative is the design of reusable intellectual property. "We are enhancing our IP development and productizing capabilities and expanding our work in the areas of connectivity peripherals. Existing competencies in the reuse IP portfolio will be leveraged to provide SoC integrators with ready-to-use subsystems, which can be plugged to build complex SoCs," de Vries said.

Philips' relationship with STMicroelectronics and Freescale Semiconductor is to be expanded to include more high-level circuit blocks, and the center here is set to have a key role.

Philips Semiconductors has 500 staffers here, and hiring will continue.