nSys Demonstrates Verification IP for PCIe 3.0 at the PCI-SIG DevCon 2009
-- nSys Design Systems will demonstrate Verification IP for PCIe® 3.0, which is currently at preliminary revision 0.5, at the PCI-SIG® DevCon 2009, to be held in Santa Clara, CA on July 15-16, 2009.
“In our endeavor to take PCI to the next generation, we have consistently relied upon PCI-SIG member companies including nSys as part of the PCIe ecosystem,” said Al Yanes, chairman and president, PCI-SIG. “nSys has been actively sponsoring PCI-SIG developers conferences around the world for more than five years now and we appreciate their willingness to share their experiences and expertise by presenting papers that benefit other members.”
“nSys has a comprehensive Verification IP for PCIe 2.0/ 1.0, in native Verilog and SystemVerilog,” said Atul Bhatia, CEO, nSys Design Systems. “As PCIe 3.0 is still evolving, it is our endeavor as an observer of the protocol working group, to make available the interim solutions for Verification IP to industry leaders.”
About nSys
nSys leverages the world’s largest portfolio of Verification IPs it has developed, to provide products & services to Accelerate Designs for its customers developing ASIC, FPGA or IP. The nVS family has proven Verification IPs in SystemVerilog and Verilog for standard interfaces/protocols such as PCI Express, SATA, SAS, AXI, AHB, APB, USB 2.0, SuperSpeed USB 3.0, DDR2, DDR3, Ethernet etc. For more information, please visit nSys online at www.nsysinc.com
About PCI-SIG
The PCI Special Interest Group (PCI-SIG) actively promotes PCI technology through a series of events. Members can test products at compliance workshops, receive PCI training at technical update seminars, participate in industry education and aid in promoting PCI technology at select tradeshows. For further information visit www.pcisig.com
Related Semiconductor IP
- PCI Express Verification IP
- PCI Express Synthesizable Transactor
- PCI Express to AMBA 4 AXI/3 AXI Bridge
- Multi-Port Switch IP for PCI Express
- IDE Security IP Modules for PCI Express 7.0
Related News
- PLDA Announces Integration of their PCIe 3.0 Controller IP into Kazan Networks' NVMe Over Fabric Fuji ASIC, Providing a Dramatic Increase in Scalability and Flexibility for Storage Applications
- USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP Cores for High Bandwidth, Low Power data communication in PCs, Mobiles, SSDs, and other Multimedia Devices.
- USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP cores with Superfast speed and High-power efficiency for lag-less data processing is Silicon Proven and available in 8nm LPP for licensing
- USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP in 12nm, 16nm and 22nm process nodes with simple integration and flexible customization is ready for immediate licencing for your advanced SoC design
Latest News
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- The world’s first open source security chip hits production with Google
- ZeroPoint Technologies Unveils Groundbreaking Compression Solution to Increase Foundational Model Addressable Memory by 50%
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- AheadComputing Raises $21.5M Seed Round and Introduces Breakthrough Microprocessor Architecture Designed for Next Era of General-Purpose Computing