Sidense Achieves Working Embedded OTP at 65nm

Embedded Non-Volatile Memory IP Ideal for High-Volume, Cost-Effective Solutions

Ottawa, Canada - Nov 12^th, 2007 - Sidense, a leading developer of Logic Non-Volatile Memory (NVM) IP cores, today announced it has successfully achieved functional embedded NVM at 65nm silicon and will complete full qualification in Q1 of 2008. The initial 65nm offering includes standard/general and low power/leakage processes.

Many high-volume applications are migrating to 65nm and smaller processes. One difficulty chip designers face at these advanced process nodes is finding scalable non-volatile storage solutions. Charge-storage NVM products suffer from data retention issues in standard-logic CMOS process nodes at 65nm and below. Sidense's patented anti-fuse technology does not suffer from these data retention problems and scales to geometries below 45nm.

"Many customers have expressed excitement about our technology, which provides them with a low-power, reliable, and cost-effective path to 65nm, 45nm and beyond," said Xerxes Wania, President and CEO of Sidense. "With our OTP memory IP, our customers can develop competitive products for a broad range of applications."

65nm applications are price sensitive and Sidense’s patented 1T-Fuse^TM provides the industry’s smallest NVM bit cell, leading to highly cost-effective solutions. Additionally, the technology can be manufactured on a standard-logic CMOS process with no additional masks or process steps.

This latest product offering enhances Sidense’s broad NVM product portfolio, which is currently available from 180nm to 65nm at leading foundries.

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