Mosys' 1T-SRAM-Q technology silicon validated on 0.13-micron logic process

Highest density of any embedded high-performance RAM  

SUNNYVALE, Calif., September 2, 2003 – MoSys, Inc. (NASDAQ: MOSY), the industry’s leading provider of high density embedded memory solutions, announced today the successful silicon validation of its 1T-SRAM-Q™ (Quad density) embedded memory technology on the 0.13-micron logic process.  With a complete macro density of 1.1-square millimeters per megabit, 1T-SRAM-Q technology enables designers to embed even larger high-performance memories in their SoC designs.  1T-SRAM-Q incorporates MoSys’ proprietary Transparent Error Correction™ (TEC™) technology delivering the additional benefits of improved yield and reliability with elimination of laser repair and soft error concerns.

“Following the adoption of 1T-SRAM-Q by the leading semiconductor foundries, this achievement shows MoSys’ continued commitment to develop the best in memory technology and also validate that technology on today’s leading manufacturing processes,” commented Dr. Fu-Chieh Hsu, president and CEO of MoSys. “Now SoC designers can integrate over 100 megabits of high performance embedded memory in 0.13-micron designs”

1T-SRAM-Q memory is based on MoSys’ patented Folded Area Capacitor™ (FAC™) technology to reduce bit cell size by literally folding the bit cell gate oxide capacitor vertically down the STI sidewall thus dramatically reducing the horizontal area.  This results in typical bit cell sizes of 0.5 and 0.28 squared micron for the 0.13-micron and 90-nanometer process nodes respectively.  A comprehensive silicon characterization report for 0.13-micron 1T-SRAM-Q is now available from MoSys.

ABOUT MOSYS AND 1T-SRAM
Founded in 1991, MoSys (NASDAQ: MOSY), develops, licenses and markets innovative memory technologies for semiconductors. MoSys' patented 1T-SRAM technologies offer a combination of high density, low power consumption, high speed and low cost unmatched by other available memory technologies. The single transistor bit cell used in 1T-SRAM memory results in the technology achieving much higher density than traditional four or six transistor SRAMs, while using the same standard logic manufacturing processes.       

1T-SRAM technologies also offer the familiar, refresh-free interface and high performance for random address access cycles associated with traditional SRAMs. In addition, these technologies can reduce operating power consumption by a factor of four compared with traditional SRAM technology, contributing to making it ideal for embedding large memories in System on Chip (SoC) designs. MoSys’ licensees have shipped more than 50 million chips incorporating 1T-SRAM embedded memory, demonstrating the excellent manufacturability of the technology in a wide range of silicon processes and applications. MoSys is headquartered at 1020 Stewart Drive, Sunnyvale, California 94085. More information is available on MoSys' Web site at http://www.mosys.com.
 

1T-SRAM® is a MoSys trademark registered in the U.S. Patent and Trademark Office.  All other trade, product, or service names referenced in this release may be trademarks or registered trademarks of their respective holders.

"Safe Harbor" Statement under the Private Securities Litigation Reform Act of 1995: Statements in this press release regarding MoSys, Inc.'s business which are not historical facts are "forward-looking statements" that involve risks and uncertainties. For a discussion of such risks and uncertainties, which could cause actual results to differ from those contained in the forward-looking statements, see "Risk Factors" in the Company's Annual Report or Form 10-K for the most recently ended fiscal year.