M31 Validates MIPI M-PHY v5.0 IP on 4nm, Advances 3nm Development to Enable UFS 4.1 Applications
Hsinchu, Taiwan — Feburay 23, 2026 — M31 Technology (M31), a global leader in silicon intellectual property (IP), today announced that the silicon-proven MIPI M-PHY v5.0 IP has been validated on an advanced 4nm process node and is actively advancing development toward the 3nm node. This milestone demonstrates M31’s core technical capability to enable UFS 4.1 (Universal Flash Storage) through a comprehensive high-speed storage interface solution, addressing the growing performance demands of flagship smartphones, automotive smart cockpits, and AI edge computing devices.
As AI and autonomous driving technologies continue to advance at a rapid pace, end devices are experiencing exponential growth in demand for data throughput. The MIPI M-PHY v5.0 IP introduced by M31 strictly complies with MIPI Alliance specifications and delivers per-lane data rates of up to 23.32Gbps in HS-G5 (High Speed Gear 5) mode—doubling the performance of the previous HS-G4 generation. The IP integrates adaptive equalization (Adaptive EQ) and multi-amplitude signaling support, ensuring excellent signal integrity and a low bit error rate (BER) even at high data rates. In addition, an optimized hibernate mode effectively extends battery life in end devices, achieving an optimal balance between high performance and low power consumption.
Explore MIPI M-PHY IP:
- MIPI MPHY v4.1, 2Tx-2Rx Type-1, TSMC N5A, 1.2V, N/S orientation(ASIL-B)
- MIPI MPHY v4.1, 2Tx-2Rx Type-1, TSMC N6, 1.8V, N/S orientation(ASIL-B)
To further accelerate SoC development cycles, M31 has built a comprehensive UFS solution. In addition to the physical layer (PHY), the solution integrates a JEDEC-compliant UFSHCI v4.1 controller IP and a UniPro control layer IP. This one-stop solution significantly reduces integration complexity and incorporates ISO 26262 functional safety design processes and certification, meeting the requirements of automotive and high-reliability end applications.
“In the wave of AI deployment and automotive intelligence, M31 leverages its deep expertise in high-speed interface IP to deliver silicon-proven M-PHY v5.0 performance on 4nm,” said Jerome Hung, Vice President of RD at M31. “By combining this with a fully integrated UFS 4.1 controller solution, we continue to expand our presence in advanced process technologies and automotive safety standards, positioning M31 as a trusted technology partner for next-generation high-speed storage platforms.”
Related Semiconductor IP
- MIPI MPHY v4.1, 2Tx-2Rx Type-1, TSMC N5A, 1.2V, N/S orientation(ASIL-B)
- MIPI MPHY v4.1, 2Tx-2Rx Type-1, TSMC N6, 1.8V, N/S orientation(ASIL-B)
- MIPI M-PHY
- Simulation VIP for MIPI M-PHY
- MIPI M-PHY HS Gear 4 IP
Related News
- M31 Announces MIPI M-PHY Passes TSMC IP Validation Center Program
- Aviacomm adopts M31 MIPI M-PHY IP for 4G-LTE RF transceiver solutions for mobile devices
- M31 MIPI M-PHY is certified with ASIL-B safety level of ISO 26262 to provide safe and reliable automotive SoC design
- MIPI UFS v3.1 Ctrl., MIPI UniPro v1.8 Ctrl. & MIPI M-PHY v4.1 IP Cores in 12nm & 28nm available for immediate licensing for high performance serial interface applications
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