Low-power design goes mainstream

Advanced process technologies, rising clock rates and increased circuit complexity have meant an end to traditional methods of managing power consumption. Engineers can no longer expect to achieve power-efficient designs with a quick power calculation and a liberal dose of decoupling capacitors. Instead, they need to routinely apply sophisticated low-power design methods that can address the rising impact of power problems in nanometer designs at 130 nm and below.

In the past, low-power design specialists have used such techniques as clock gating, frequency scaling, novel processes or libraries, and even more-sophisticated techniques such as voltage scaling and multithreshold cell optimization. For the typical designer, however, many of these methods have been relatively inaccessible or impractical.

The growing availability of enhanced tools, models and processes-all highly matched and expressly created for low-power design-has begun to put more-effective low-power design capabilities in the hands of mainstream designers. Today, successful strategies for low-power design are extending familiar design flows with more-effective models, detailed analysis techniques and careful consideration of effects like IR drop and electromigration. In using these power-optimized design flows, designers will need to adhere to several key design principles found through experience to significantly enhance low-power design success.

Do

• Show the synthesis tool as many choices of library cells at different threshold voltages (Vth) as possible, to achieve an optimal trade-off among performance, leakage and dynamic power. Cells with higher Vth exhibit less leakage current than those with lower Vth, but also higher cell delay, degrading overall performance. When synthesis tools can consider a wider choice of Vth cells, they can more effectively provide a netlist implementation at the lowest possible leakage current.
• Perform power analysis as early as possible and keep in mind the effects of voltage scaling. If the performance target remains constant, voltage scaling carries an implied trade-off between dynamic-power savings and leakage-power savings. As voltage is reduced, the cell will be slower and there will be less opportunity to use low-leakage cells.
• Identify all opportunities for clock gating, in which a gating circuit shuts off the clock for registers that do not need to be loaded on a particular clock cycle. Ideally, the design should be viewed as virtually flat, without hierarchical boundaries to share the enabling control logic.
• Consider the impact of IR drop on timing, especially with a voltage-scaled design. The timing-delay impact of 1-mV Vdd drop on a 90-nm G process could be greater than 30 percent. Also, consider the effect of electromigration when routing the power supply to special isolation cells.
• Use a current source delay model, such as the Effective Current Source Model, for multisupply-voltage designs. ECSM offers very accurate delay information (within 0.5 percent of Spice models) and a simplified analysis methodology.
• Use formal verification throughout the design flow to ensure design integrity and equivalency.

Don't

• Insert decoupling capacitors randomly and excessively. Decoupling capacitance acts as a charge source to smooth out the switching spikes, but it is also a source of leakage current. Too much decoupling capacitance or having it at the wrong place will be more costly in terms of static power consumption than the benefit to dynamic power. Instead, perform dynamic-power analysis to identify the optimal location and value of the decoupling capacitance.
• Intermix the placement of level shifters with other standard cells. This will require complex routing to the special power connections and increase the impact on signal crosstalk due to the differing voltage charge.
• Forget to analyze power dissipated during test mode. Some test modes may actually dissipate more power than normal operation as they attempt to toggle and observe as many nodes as possible.
• Rely on traditional analysis methods using simple derating of supply voltage in calculating timing performance. Such methods can introduce significant error due to linear derating that often exceeds 20 percent from Spice, particularly for the slower low-power cells.
• Analyze the design timing block by block. With MSV design, timing accuracy is much more demanding, so timing analysis across different power domains is needed to ensure proper optimization and accuracy. Also, do not assume that traditional hierarchical modeling methods for each island are accurate enough for the advanced-technology nodes.

George Kuo (gkuo@cadence.com), engineering director for design chain initiatives at Cadence Design Systems Inc.(San Jose, Calif.)