LogicVision Showcases High-Speed I/O Test Technology at SEMICON West Conference
Company’s Breakthrough Technology Selected for Prestigious Technology Innovation Showcase
SAN JOSE, Calif. — July 8, 2005 — LogicVision, Inc. (NASDAQ: LGVN), a leading provider of yield learning capabilities that enable its customers to quickly and efficiently improve product yields, today announced its innovative high speed embedded SerDes I/O test technology has been selected as one of the emerging technologies to be highlighted in the Technology Innovation Showcase (TIS) at SEMICON West, July 12 – 14. The TIS will be located in the Emerging Technologies Hall, Esplanade, at Moscone Center in San Francisco. TIS winners are selected by a jury of technologists for the promise their innovations hold for the future of microelectronics and nano-electronics manufacturing.
The TIS includes technical presentations and an exhibit pavilion featuring displays from each of the participating companies and organizations. Stephen Sunter, an engineering director at LogicVision, will be presenting Embedded SerDes Test on the TIS stage on Thursday July 14th at 12:50pm.
LogicVision’s Embedded SerDes Test (EST) product is an IP-based technology that provides unique capabilities for testing ICs with an unlimited number of high-speed serial data channels operating at any frequency, from less than 1 Gbps to more than 10 Gbps. EST provides test accuracy comparable to that of the highest performance external equipment, but is compatible with any ATE platform. The ability of EST to diagnostically measure waveshape, jitter, and jitter tolerance, in millisecond test times, can improve yield and quality, and reduce test cost. The technology has been verified in silicon on SerDes channels running over 3 Gbps.
About LogicVision Inc.
LogicVision, Inc. (NASDAQ: LGVN), provides unique yield learning capabilities in the design for manufacturing space. These capabilities enable its customers, leading semiconductor companies, to more quickly and efficiently learn to improve product yields. The company’s advanced Design for Test (DFT) product line, ETCreate, works together with ETAccess and SiVision yield learning applications to enable increased profit by reducing device field returns, reducing test costs, and accelerating both time to market and time to yield. LogicVision solutions are used in the development of semiconductor ICs for products ranging from digital consumer goods to wireless communications devices and satellite systems. LogicVision was founded in 1992 and is headquartered in San Jose, Calif. For more information visit www.logicvision.com.
FORWARD LOOKING STATEMENTS:
Except for the historical information contained herein, the matters set forth in this press release, including statements as to the expected features and benefits of the company’s products and technology, such as improvements in yield and quality and reductions in test costs, are forward-looking statements within the meaning of the Private Securities Litigation Reform Act of 1995. These forward-looking statements are subject to risks and uncertainties that could cause actual results to differ materially, including, but not limited to, the impact of competitive products and technological advances, including changes in ATE platforms, and other risks detailed in Form 10-Q for the quarter ended March 31, 2005, and from time to time in LogicVision's SEC reports. These forward-looking statements speak only as of the date hereof. LogicVision disclaims any obligation to update these forward-looking statements.
LogicVision, Embedded SerDes Test, LogicVision Ready and LogicVision logos are trademarks or registered trademarks of LogicVision Inc. in the United States and other countries. All other trademarks and service marks are the property of their respective owners.
Related Semiconductor IP
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- All Digital Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 22FDX
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- TSMC CLN5FF GUCIe LP Die-to-Die PHY
Related News
- AccelerComm Secures $15m Funding to Speed Adoption of Technology for Space-Based 5G Networks to Deliver Universal Mobile Coverage
- Alphawave Semi at the Forefront of PCIe® 7.0 Specification: Showcasing Next-Gen Chiplet Interoperability and Optical PCIe Technology at PCI-SIG® Developers Conference 2025
- OPENEDGES Collaborates with Renesas on Memory Subsystem IPs for Next-Generation MPU Platform Development
- M31 Ranked in the Top 5% of TPEx-Listed Companies in the Corporate Governance Evaluation for Four Consecutive Years
Latest News
- SEMIFIVE Files for Pre-IPO Review on KRX
- Innosilicon Scales LPDDR5X/5/4X/4 and DDR5/4 Combo IPs to 28nm and 22nm, Cementing Its Position as the ‘One Stop’ for Memory Interface Solutions
- Synopsys Completes Acquisition of Ansys
- Zephyr 4.0 Now Available for SCR RISC-V IP
- Lattice Semiconductor and Missing Link Electronics Become Partners to Accelerate FPGA Design Projects