Andes Technology Launches RISC-V Now! — A Global Conference Series Focused on Commercial, Production-Scale RISC-V

A practitioner-focused forum on system architecture, silicon decisions, and shipping production platforms

San Jose, Calif. — Feb. 3, 2026 – Andes Technology (TWSE: 6533), a leading supplier of high-efficiency, low-power RISC-V processor cores and Founding Premier member of RISC-V International, today announced the launch of RISC-V Now! by Andes, a global conference series focused on the realities of deploying RISC-V in production systems.

As AI workloads, power constraints, cost pressures, and long-term platform control reshape compute design, many organizations are reassessing CPU and SoC strategy. RISC-V Now! was created to address these challenges directly, bringing together practitioners to share real-world experience from systems that are shipping today.

The Silicon Valley event will take place April 20–21, 2026, at the DoubleTree by Hilton San Jose, convening system architects, silicon leaders, and executives building and deploying RISC-V-based production platforms across AI, automotive, data center, networking, and embedded markets. Additional events will take place in Hsinchu (April 15), Shanghai (May 12), and Beijing (May 14).

“RISC-V’s next phase is about shipping systems,” said Frankwell Lin, Chairman and CEO of Andes Technology. “Performance, power efficiency, software integration, and system-level optimization are what turn an open ISA into a production platform. RISC-V Now! by Andes focuses on what it actually takes to deploy RISC-V successfully in real products.”

Built for Deployment-Focused Teams

Designed to complement standards- or ecosystem-focused forums, RISC-V Now! is optimized for organizations moving from evaluation to production. The program emphasizes:

• System-level trade-offs in shipping AI and compute platforms
• CPU and SoC strategy under power, cost, and scaling constraints
• Software enablement challenges encountered in real deployments
• Lessons learned—what worked, what didn’t, and what teams wish they had known earlier

RISC-V Now! evolves Andes’ long-running RISC-V CON events, which last year attracted more than 1,100 registrations and 550 in-person attendees globally, with a senior audience dominated by engineering leadership and CXO-level decision-makers. The new format sharpens the focus on execution and deployment-grade insight.

“As I attend RISC-V ecosystem events around the world,  I see a focus increasingly shifting to industry implementation and execution. What matters is how open standards translate into scalable, production-ready platforms, strong software ecosystems, and long-term sustainability,” said Andrea Gallo, CEO of RISC-V International.  “Initiatives like RISC-V Now! by Andes play an important role by bringing together the global community around real-world deployment and commercial experience.”

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A Signal Event for Sponsors

RISC-V Now! is intentionally designed as a signal event, not a volume event. Sponsorship opportunities are limited and focused on companies enabling or depending on production-grade compute platforms, offering direct access to a highly curated audience making long-term architecture decisions.

“We’re seeing strong customer demand for production-ready RISC-V platforms, and the conversations that matter now are about deployment, integration, and scale,” said Oliver Jones, CEO of Aion Silicon. “RISC-V Now! brings together exactly the architects and decision-makers we want to engage, which is why we chose to participate as a sponsor.”

More information, including speaking and sponsorship opportunities, is available at www.riscv-now.com.

RISC-V Now! is produced and underwritten by Andes Technology and extends its multi-year investment in the RISC-V ecosystem, complementing broader industry initiatives by focusing on commercialization, deployment, and execution.

About Andes Technology

As a Founding Premier member of RISC-V International and a leader in commercial CPU IP, Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) is driving the global adoption of RISC-V. Andes’ extensive RISC-V Processor IP portfolio spans from ultra-efficient 32-bit CPUs to high-performance 64-bit Out-of-Order multiprocessor coherent clusters. With advanced vector processing, DSP capabilities, the powerful Andes Automated Custom Extension (ACE) framework, end-to-end AI hardware/software stack, ISO 26262 certification with full compliance, and a robust software ecosystem, Andes unlocks the full potential of RISC-V, empowering customers to accelerate innovation across AI, automotive, communications, consumer electronics, data centers, and mobile devices. Over 19 billion Andes-powered SoCs are driving innovations globally. Discover more at www.andestech.com.