MIPS at 40
Interview with CEO Sameer Wasson at CES 2025.
By David Harold, JPR (January 24, 2025 )
MIPS is celebrating its 40th anniversary as a compute IP company this year. Known for a RISC instruction set, the company has risen and fallen, was private, then owned by SGI, was private again for a while, then Imagination Technologies owned it for several years, sold to a VC, Tallwood, in 2017, and then owned by Wave Technologies briefly before returning to the same VC hands.
In March 2021, MIPS announced that it would cease development of the MIPS architecture as was and transitioning to RISC-V designs. This move marked the end of an era for the MIPS architecture and signaled the company’s adaptation to changing market demands. Most notably, they delivered a high-performance compute with simultaneous multi-threading (SMT) licensed to Mobileye. JPR’s David Harold met with MIPS CEO Sameer Wasson to discuss the company’s progress and strategy.
To read the full article, click here
Related Semiconductor IP
- RISC-V Debug & Trace IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- Compact Embedded RISC-V Processor
- Multi-core capable 64-bit RISC-V CPU with vector extensions
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
Related News
- CEO interview: MIPS' Sameer Wasson on a RISC-V reboot
- CEO Interview: Sameer Wasson of MIPS -- "Have a Steady Hand, Don't be Distracted"
- New MIPS CEO Sameer Wasson to Drive Company's RISC-V Market Penetration and Innovation
- CEO interview: S3 Semi ready for custom opportunity
Latest News
- Global Semiconductor Sales Increase Substantially in February
- Hardware Root of Trust Essential for AI Chip Integrity
- AI Compute Demand Drives 44% YoY Growth for Top 10 Global Fabless IC Firms in 2025
- IBM Announces Strategic Collaboration with Arm to Shape the Future of Enterprise Computing
- Rambus Unveils HBM4E Controller: 16 GT/s, 2,048-Bit Interface, Enabling C-HBM4E