Intel readies scaleable StrongArm processors for handheld systems
Intel readies scaleable StrongArm processors for handheld systems
By Mark LaPedus, Semiconductor Business News
August 23, 2000 (10:05 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000823S0003
San Jose -- Intel Corp. here today will expand its efforts in the handheld chip market by announcing its second-generation processor for cellular phones, personal digital assistants (PDAs), and related systems. The new XScale product, which is an updated version of Intel's StrongArm RISC-based processor series, is a flexible, low-power device designed to handle clock speeds up to 1 GHz, according to Ronald Smith, vice president and general manager of the company's Wireless Communications & Computing Group, headquartered in Folsom, Calif. Intel will begin showing samples of the XScale at the Intel Developer Forum (IDF) in San Jose today, and it plans to ship a 600-MHz version of the chip by year's end, said Smith said. "The XScale is an extension to the StrongArm, with a much broader range of performance," Smith said. Intel's XScale disclosure at IDF is not a product announcement, but rather an effort to give system developers information about the new, super-pipelined architecture for the StrongArm. This super-pipelined architecture is designed to meets the requirements of current and future handheld devices, Smith said. A key element in the XScale architecture is a feature called Dynamic Voltage Management, which enables the RISC-based chip to support various clock speeds and power-consumption levels. "Voltage and power can change on the fly with this chip," Smith explained. In other words, XScale is a scaleable architecture. At the high-end, the chip can be tuned to support 1-GHz clock rates with power consumption of just 1.5 watts, according to Intel. At the low-end, the XScale chip could support a 200-MHz clock rate with power consumption of only 40 millwatts, said the Santa Clara, Calif.-based processor giant. The first chip to be introduced in the market will be a 600-MHz device with a power consumption of 0.50 watts, according to Smith. The 600-MHz chip is expected to hit the streets by year's end, Smith added in a pre-an nouncement briefing on Tuesday.
Related Semiconductor IP
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- 10-bit Pipeline ADC - Tower 180 nm
- NoC Verification IP
- Simulation VIP for Ethernet UEC
- Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
Related News
- Andes Technology Partners with WITTENSTEIN high integrity systems (WHIS) to Build Safety-Critical Solutions with RISC-V Processors
- Breker Verification Systems Readies RISC-V CoreAssurance and SoCReady SystemVIP for Automated, Certification-level RISC-V Verification Coverage
- Senior Intel CPU architects splinter to develop RISC-V processors - veterans establish AheadComputing
- ARM Licenses Jazelle Software To SavaJe To Accelerate JAVA For Embedded And Handheld Devices
Latest News
- Presto Engineering Group Acquires Garfield Microelectronics Ltd, Creating Europe’s Most Comprehensive ASIC Design to Production One-Stop-Shop
- Qualitas Semiconductor Demonstrates Live of PCIe Gen 6.0 PHY and UCIe v2.0 Solutions at ICCAD 2025
- WAVE-N v2: Chips&Media’s Custom NPU Retains 16-bit FP for Superior Efficiency at High TOPS
- Quintauris releases RT-Europa, the first RISC-V Real-Time Platform for Automotive
- PQShield's PQCryptoLib-Core v1.0.2 Achieves CAVP Certification for a broad set of classical and post-quantum algorithms