How do you count cores? Or should you?
Jim McGregor
EETimes (3/6/2012 6:40 AM EST)
As we enter 2012, we know that many new processor introductions are on the horizon. Intel will be introducing its new platforms for PCs and servers, ARM will be formally announcing a 64-bit architecture, and many of the ARM partners will be introducing new processors based on the various Cortex cores and core combinations. This is all good news for the industry as whole as we strive to increase performance while maintaining or decreasing costs and power consumption.
So far, the number of cores, or CPU cores to be more specific, has been a very important factor in the industry. Increasing core counts has allowed us to increase overall performance while avoiding the thermal limitations of running a single core processor faster. Increasing core counts has also provided a simple benchmark for comparing products.
To read the full article, click here
Related Semiconductor IP
- CXL 3.0 Premium Controller EP/RP/DM/SW 128-1024 bits with AMBA bridge and Advanced HPC Features (Arm CCA)
- CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge and Advanced HPC Features (Arm CCA)
- 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- 32b/64b RISC-V 2-stage, scalar, in-order, Embedded Processor. RTOS and multi-core capable. Maps upto ARM M-4F. Optimal PPA.
- PCIe 6.0 (Gen6) Premium Controller EP/RP/DM/SW 128-1024 bits with AMBA bridge and Advanced HPC Features (Arm CCA)
Related News
- How bad is IP theft in China? And what can you do about it?
- Intel's 22-nm tri-gate SoC, how low can you leak?
- How Secure Is Your USB?
- MIPI RFFE (RF Front-End Control Interface) v3.0 Master and Slave Controller IP Cores for ultimate control of your RF Front-end Cellular or Base station SoC's with Low Power Consumption and Reduced Latencies
Latest News
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- The world’s first open source security chip hits production with Google
- ZeroPoint Technologies Unveils Groundbreaking Compression Solution to Increase Foundational Model Addressable Memory by 50%
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- AheadComputing Raises $21.5M Seed Round and Introduces Breakthrough Microprocessor Architecture Designed for Next Era of General-Purpose Computing