Fujitsu to Construct New Fab for Logic Chips Employing 65nm Process Technology and 300mm Wafers

Second 300mm facility boosts production capacity at Mie semiconductor plant

Tokyo, January 11, 2006 — Fujitsu Limited today announced that it will construct a new fab to mass-produce logic semiconductors employing leading-edge 65-nanometer (nm) process technology and 300 millimeter (mm) wafers. The fab will be constructed at Fujitsu's Mie semiconductor plant, in Mie prefecture of central Japan, as the second 300mm fab of the plant and will be referred to as 300mm Fab No.2. In addition to accommodating increasing demand for semiconductors produced using advanced processes through construction of the new fab, by continuing to offer optimized solutions and high-performance products based on leading-edge technologies, Fujitsu will continue to be a trusted business partner to its customers.

300mm Fab. No.2, which will feature a dual-level clean room structure, is scheduled to be constructed within fiscal 2006 (April 2006 - March 2007) and become operational from April 2007, with volume shipments expected to start from July 2007.

During the two year period till the end of fiscal 2007, Fujitsu will invest approximately 120 billion yen in the new fab and production capacity will reach 10,000 wafers per month. Further investments will be made in stages as the company evaluates trends in market demand. Fujitsu expects the maximum capacity of the facility will be 25,000 wafers per month.

300mm Fab. No.1, the first 300mm fab that was constructed at the Mie plant with a line for mass production of 300mm wafers employing 90nm technology, has been operational since April 2005 and will reach a production capacity of 15,000 wafers per month in fiscal 2006.

Fujitsu has been highly appraised by its customers for its ability to offer advanced process technologies which realize high-speed operation and low power consumption simultaneously, a competitive edge made possible by its transistor technologies and copper wiring and low-K(1) process technologies, in addition to receiving high marks for its design methodologies(2) which enable first-shot full operation(3) . Fujitsu is continuously in negotiations with various global technology partners, and expects that from fiscal 2007, demand will significantly exceed the production capacity of its currently operating 300mm Fab. No.1.

By constructing the 300mm Fab No.2 with a dual-level clean room structure capable of easy expansion of capacity, Fujitsu will ensure a stable supply of leading-edge logic chips to its customers.

Overview of 300mm Fab No.2

  • Process Technologies: 65nm and 90nm CMOS Logic

  • Wafer Diameter: 300mm

  • Structural Features: Seismic-vibration control construction; clean room area: 24,000 sq. meters (At maximum capacity)

  • Production Capacity: 10,000 wafers per month (Projection for fiscal 2007); maximum capacity of 25,000 wafers per month

  • Planned Start of Operation: April 2007

Overview of 300mm Fab No.1

  • Process Technologies:90nm and 65nm CMOS Logic

  • Wafer Diameter: 300mm

  • Structural Features: Seismic-control construction; Clean room area: 12,000 sq. meters

  • Production Capacity: 15,000 wafers per month (within fiscal 2006)

  • Start of Operation:April 2005

Overview of the Mie Plant

  • Location:Kuwana city, Mie prefecture, Japan

  • Employees: Approximately 1,400 employees (including affiliated companies)

  • Main Products:90nm, 130nm and 180nm technology COTs, ASICs, ASSPs, MCUs

About Fujitsu

Fujitsu is a leading provider of customer-focused IT and communications solutions for the global marketplace. Pace-setting device technologies, highly reliable computing and communications products, and a worldwide corps of systems and services experts uniquely position Fujitsu to deliver comprehensive solutions that open up infinite possibilities for its customers' success. Headquartered in Tokyo, Fujitsu Limited (TSE: 6702) reported consolidated revenues of 4.7 trillion yen (US$44.5 billion) for the fiscal year ended March 31, 2005. For more information, please see www.fujitsu.com

Glossary

1: low-K: A layered insulating material having a low specific dielectric constant. Effective for reducing capacitance within interconnect layers, the leading-edge technology is used to realize ultra high-speed operation and low power consumption.

2: Design methodology: Method for designing leading-edge large-scale integrated circuits (LSIs) within a short period of time.

3: First-shot full operation: Design methodology for advanced LSIs which enables full functionality from initial trial chips.

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