Faraday Launches Universal Programmable SerDes IP

-- Faraday Technology Corporation (TAIEX: 3035), a leading ASIC and Silicon IP provider, today announced the availability of its programmable SerDes IP . The high-performance interface solution is designed to meet industry requirements in terms of reduced die sizes and significant power savings, which further leads the customers to a more competitive and advantageous market position.

Traditional parallel bus has faced a severe challenge in higher speed transmission due to its limited extensibility, bandwidth, and the media/cable length. Therefore, the serial-transmission technique, on which many emerging I/O standards are based, is developed. In order to support various emerging serial interface standards and some customers' proprietary requirements, a programmable SerDes IP is ardently required for this industry.

"In the past, Faraday has successfully developed multiple generations of PHY Layer IPs for serial interface standards and has assisted many customers to solidify their market positions in time. This latest SerDes technology can help designers to save tremendous development cost in PHY Layer and thus concentrate on their specific product development catering for various applications," said Dr. George Hwang, Vice President of RD & International Business at Faraday. "This Programmable SerDes IP is a milestone for Faraday team and our customers, and we will continue developing more advanced and market-driven interconnection techniques to fulfill our customers' needs."

About Faraday SerDes IP (Product flyer download)

• Applications & supporting standards : This programmable SerDes IP can be used in many fields, including Networking, Computing, and Storage markets. For the Networking market, it supports Giga-bit Ethernet, 10 Giga-bit Ethernet, and 1/2/10 G FiberChannel. For the Computing and PC peripheral markets, it supports Serial ATA and PCI Express standards. Also, for the chip-to-chip and backplane transceiver market, it supports the popular XAUI (4x 3.125G ) and Rapid I/O.

• Process & specific design: Faraday's SerDes IP(FXUPST001HC0H) is target for UMC 0.13um CMOS process. All required functional blocks (includes Power Pads) are contained within the macro and all pins connected to external pads include ESD protection. Single Lane instance of the macro fits underneath 12 contiguous pads without occupying any core areas. In addition, while defining the IP architecture, Faraday has considered its production test and the functional test capabilities, which helps designers to shorten testing time, save cost, and enhance the competitiveness.

• Transmitting speed: The programmable SerDes IP is suitable for applications with variable speed ranging from 1Gbps to 3.125Gbps to cover the need of dominant high-speed transmitting interface.

Faraday Technology Corporation is a leading silicon IP and fabless ASIC vendor. The company's broad SIP portfolio includes 32-bit RISC CPUs, DSPs, MPEG4, H.264, PHYs/Controllers for USB 2.0, 10/100 Ethernet, Serial ATA, PCI Express, Cell Library and Memory Compiler. With more than 650 employees and 2005 revenue of US$175 million, Faraday is one of the largest fabless ASIC companies in the Asia-Pacific region, and it also has a significant presence in other world-wide markets. Headquartered in Taiwan , Faraday has service and support offices around the world, including the U.S. , Japan , Europe, and China . For more information, please visit : www.faraday-tech.com