Faraday looks to play in structured ASICs

Faraday looks to play in structured ASICs
By Mike Clendenin, EE Times
June 13, 2003 (3:09 p.m. EST)
URL: http://www.eetimes.com/story/OEG20030613S0029

TAIPEI, Taiwan — Taiwan design services outfit Faraday Technology Corp. is joining the structured ASIC movement, and adding a few twists to its offering that it claims sets it apart from the rest of the pack.

Faraday (Hsinchu, Taiwan) has codenamed its offering 3MPCA, or Three-Mask Programmable Cell Array, and will offer it on CMOS processes from foundry UMC, ranging from 0.35 micron to 0.13 micron. A 90nm version is in the works. The company also has a handier brand name for the architecture—Flexible ASIC.

This latest trend in ASIC design holds the promise of compromise between higher cost, standard cell-based ASICs and the performance and flexibility of FPGAs. With its offering, Faraday joins the ranks of a handful of companies in the slowly growing structured ASIC segment, including AMI Semiconductor (Pocatello, Idaho,) Chip Express (Santa Clara, Calif.,) Lightspeed Semiconductor (Sunnyvale, Calif.) and NEC.

All believe customer s will be attracted by the faster time to market of the structured ASIC approach, and the lower non-recurring engineering costs, which will more than double from 0.13 micron to 0.09 micron for standard ASICs.

Customers anticipating frequent changes to the chip's functionality and those with low- to mid-volume run ASICs may also opt for this approach. In essence, that's a wide swath of the ASIC market, said Wang Hsin-shih, senior technical director at Faraday and leader of the 3MPCA project “CPU is high volume, graphics is high volume and so is FPGA, but we don't see too many other high volume chips out there today,” he said.

The company is rolling out the new design approach as part of its greater IP offering. The company is vying with others to attract customers to its “chip level platform,” and the 3MPCA embedded logic is part of that drive. Faraday said its approach, when contrasted against standard cell design, reduces delivery time from 18 to 10 months (from RTL to back-end test).

In shor t, a structured ASIC paradigm allows companies like Faraday to order wafers with the first few metal layers already formed, then store them until a customer calls. Then that customer's design, and future changes or corrections, can be implemented in the upper metal layers; in the case of Faraday, through two metal layers and one via layer.

Because cell-based ASICs require a full set of masks, it's a tough proposition for designers to justify the cost of using an advanced 0.13 micron process for a low-volume product. The structured ASIC allows for a reasonable degree of user configurability without the full set of masks, said Jim Tully, semiconductor analyst with Gartner Dataquest. “That's pretty attractive,” he said, “and we believe this kind of technology will take a reasonable percentage of the ASIC market.”

Like its competitors, Faraday's approach compares with standard cell performance and power efficiency and it claims to have the industry's best array density for structured ASICs. The company is also stressing that in using two top metal layers and one top via mask to do the function programming and interconnects, its architecture is superior to one-mask programmable cell arrays, which have all their metal layers predefined. That may be true, but others, such as NEC and Chip Express, seem to be offering something similar.

Yet Faraday seems to offer several features that help differentiate it. For instance, 3MPCA can implement any type of combinational and sequential logic and it supports unlimited numbers of clock domains and gated clocks. “No other vendor is offering this kind of clocking flexibility,” Wang said.

Each of the 3MPCA blocks comprises several Look-Up-Table (LUT) cells, driving cells, and storage elements. For instance, in a generator, there can be six look-up tables, one driver cell and one flip-flop, for a 6-1-1 ratio. This is a main difference between Faraday and other vendors, Wang said.

“Other vendors put the flip flops together with the look-up tables. So they often have a 1-1 ratio. We don't think that many flip flops have to be in the logic design because the logic does more than flip flops. That's the reason we achieve much higher density,” he said.